
 /***********************************************************************************
  * @file     SD93F115B.h   						    							*																													
  * @author   TEST TEAM																*
  * @version  v0															    	*
  * @date     Septemper 2022												    	*
  * @brief    CMSIS Cortex-M0 Device Peripheral Access Layer Header File. 	    	*
  *           This file contains all the peripheral register's definitions, bits 	*
  *           definitions and memory mapping for SD93F115B devices.            		*
  *           																		* 
  *           This file contains:													*
  *           - Data structures and the address mapping for all peripherals			*	
  *           - Peripheral's registers declarations and bits definition				*		
  *           - Macros to access peripheral’s registers hardware  					*
  *																					*		
  ***********************************************************************************
  * @attention																		*
  *																					*
  *  * Copyright (C) 2022  Hangzhou SDIC Microelectronics Co., Ltd					*
  *																					*
  * Redistribution and use in source and binary forms, with or without modification,*
  * are permitted provided that the following conditions are met:					*
  *   1. Redistributions of source code must retain the above copyright notice,		*
  *      this list of conditions and the following disclaimer.						*
  *   2. Redistributions in binary form must reproduce the above copyright notice,	*
  *      this list of conditions and the following disclaimer in the documentation	*
  *      and/or other materials provided with the distribution.						*
  *   3. Neither the name of SDIC Microelectronics nor the names of its contributors*
  *      may be used to endorse or promote products derived from this software		*	
  *      without specific prior written permission.									*
  *																					*
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"		*
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE		*
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE	*
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE	*
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL		*
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR		*
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER		*
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,	*
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE	*
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.			*
  *																					*
  ***********************************************************************************/
	
#ifndef __SD93F115B_H__
#define __SD93F115B_H__

#ifdef __cplusplus
 extern "C" {
#endif 
/******************** SD931F115B封装选择 **************************/
//#define  SD93F115B_JQS        //LQFP100封装
#define  SD93F115B_D          //裸片
//#define  SD93F115B_JBS        //LQFP64封装
//#define  SD93F115B_IMR        //QFN48封装

/******************** SD93F115B specific Interrupt Numbers **************************/
typedef enum IRQn
{
  SysTick_IRQn = 0,
  LBT_IRQn = 1,
  XT1Fault_IRQn = 2,
  XT2Fault_IRQn = 3,
  FLASH_IRQn = 4,
  
  EXINT0_IRQn = 5,
  EXINT1_IRQn = 6,
  KEY_IRQn=7,
  
  UART0_IRQn = 8,
  UART1_IRQn = 9,
  I2C_IRQn = 10,
  SPI_IRQn = 11,
  
  TM0_IRQn = 12,
  TM1_IRQn = 13,
  TM2_IRQn = 14,
  
  SARADC_IRQn = 15,
  SDADC_IRQn = 16,   
 
  IWDT_IRQn = 17,
  WWDT_IRQn = 18,
  
  RTC_IRQn = 19,
  PWM0_IRQn = 20,
  PWM1_IRQn = 21
  
}IRQn_Type;

/* Configuration of the CK80# Processor and Core Peripherals */  //??????

#define __NVIC_PRIO_BITS          2       				/*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig    0      			 	/*!< Set to 1 if different SysTick Config is used */
#define __MGU_PRESENT             0      		 		/*!< MGU present or not */

/* Soft reset address */
#define  __RESET_CONST           0xabcd

/**********************************************
 * Config CPU								  *	
 * Define the attribute for your CPU		  *	
 **********************************************/
#include "CSICORE_CK801.h"

/* Exported types */
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus, RSTStatus;

typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;

typedef enum {FALSE = 0, TRUE = !FALSE} BOOL;

typedef enum{ Bit_RESET = 0,Bit_SET = !Bit_RESET} BitAction;
#define IS_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))

/******************低功耗指令定义********************/

#define  WAIT                  			 __asm("WAIT") 
#define  DOZE                  			 __asm("DOZE") 
#define  STOP                  			 __asm("STOP") 

/**************** Peripheral registers structures*******************/

/**********************EXINT*********************/		        	//EXINT  Base Address:0x4000 0000
typedef struct
{
  __IO  uint32_t CR;      				/*外部中断控制寄存器            	Address offset: 0x00 */
  __IO  uint32_t SR;      				/*外部中断状态寄存器            	Address offset: 0x04 */

 }EXINT_TypeDef;

/**********************TM**********************/  					//TM  Base Address:4000 1000/2000/3000
typedef struct
{
  __IO  uint32_t CR;        			/*!< 定时器1控制寄存器        		Address offset: 0x00 */
  __IO  uint32_t SR;        			/*!< 定时器1状态寄存器        		Address offset: 0x04 */
  __IO  uint32_t LOAD;      			/*!< 重载数据寄存器,      	  		Address offset: 0x08 */
  __IO  uint32_t CNT;       			/*!< 计数器瞬间值寄存器       		Address offset: 0x0C */
  __IO  uint32_t CCPD;      			/*!< 捕捉寄存器               		Address offset: 0x10 */
  
}TM_TypeDef;

/**********************RTC**********************/            		//RTC  Base Address:0x4000 4000 
typedef struct
{
  __IO  uint32_t CR;        			/*!< RTC控制寄存器               	Address offset: 0x00 */
  __IO  uint32_t SR; 					/*!< RTC状态寄存器               	Address offset: 0x04 */
  __IO  uint32_t TR;       				/*!< RTC时钟寄存器               	Address offset: 0x08 */
  __IO  uint32_t DR;       				/*!< RTC日期寄存器               	Address offset: 0x0C */
  __IO  uint32_t ALARMR;       			/*!< RTC闹钟寄存器             	    Address offset: 0x10 */  
  
} RTC_TypeDef;

/**********************IWDG*********************/      				//IWDG  Base Address:0x4000 5000
typedef struct
{
  __IO  uint32_t CR;        			/*!< IWDG控制寄存器         		Address offset: 0x00 */
  __IO  uint32_t SR;         			/*!< IWDG中断状态寄存器    		  	Address offset: 0x04 */
  __IO  uint32_t SETKEY;         		/*!< IWDG计数重置寄存器     	  	Address offset: 0x08 */
  
}IWDG_TypeDef;

/**********************WWDG*********************/      				//WWDG  Base Address:0x4000 6000
typedef struct
{
  __IO  uint32_t CR;         			/*!< WWDG控制寄存器    			 	Address offset: 0x00 */
  __IO  uint32_t CFR;         			/*!< WWDG配置寄存器     		 	Address offset: 0x04 */
  __IO  uint32_t SR;         			/*!< WWDG状态寄存器     		 	Address offset: 0x08 */
  
}WWDG_TypeDef;

/*******************PWM*************************/               	//PWM  Base Address:0x4000 7000/8000
typedef struct
{
  __IO  uint32_t CR;  					/*!< 控制寄存器             		Address offset: 0x00 */
  __IO  uint32_t SR; 					/*!< 状态寄存器    					Address offset: 0x04 */
  __IO  uint32_t DR;  					/*!< 数据设置寄存器     			Address offset: 0x08 */
  __IO  uint32_t TR;  					/*!< 周期寄存器     				Address offset: 0x0C */
  
} PWM_TypeDef;

/******************BUZZER***********************/            		//BUZZER  Base Address:0x4000 9000/A000
typedef struct
{
  __IO  uint32_t CR;       				/*!< 控制寄存器             		Address offset: 0x00 */
  
} BUZ_TypeDef;

/*******************I2C*************************/                    //I2C  Base Address:0x4000 B000
typedef struct
{
  __IO  uint32_t CR;        			/*!< 控制寄存器             		Address offset: 0x00 */
  __IO  uint32_t OAR;       			/*!< 本机地址寄存器         		Address offset: 0x04 */
  __IO  uint32_t BRR;         			/*!< 波特率寄存器           		Address offset: 0x08 */
  __IO  uint32_t TOR;         			/*!< 超时设置寄存器         		Address offset: 0x0c */
  __IO  uint32_t SR;         			/*!< 状态寄存器             		Address offset: 0x10 */ 
  __IO  uint32_t TXDR;         			/*!< 发送缓冲寄存器         		Address offset: 0x14 */  
  __IO  uint32_t RXDR;         			/*!< 接收缓冲寄存器         		Address offset: 0x18 */ 
 
} I2C_TypeDef;

/*******************SPI*************************/                   //SPI  Base Address:0x4000 C000
typedef struct
{
  __IO  uint32_t CR;        			/*!< 控制寄存器             		Address offset: 0x00 */
  __IO  uint32_t SR;        			/*!< 状态寄存器             		Address offset: 0x04 */
  __IO  uint32_t DR;         			/*!< 数据寄存器         			Address offset: 0x08 */
  
} SPI_TypeDef;

/*******************UART************************/                   //UART  Base Address:0x4000 D000/0x4000 E000
typedef struct
{
  __IO  uint32_t CR;        			/*!< 控制寄存器               		Address offset: 0x00 */
  __IO  uint32_t BRR;         			/*!< 波特率寄存器             		Address offset: 0x04 */
  __IO  uint32_t SR;         			/*!< 状态寄存器      		  		Address offset: 0x08 */
  __IO  uint32_t TDR;       			/*!< 数据发送寄存器           		Address offset: 0x0C */
  __IO  uint32_t RDR;       			/*!< 数据接收寄存器           		Address offset: 0x10 */ 
 
} UART_TypeDef;

/********************GPIO**********************/            		//GPIO  Base Address:0x4000 f000
typedef struct
{
  __IO  uint32_t ADR;       			/*!< 端口属性设置寄存器           	Address offset: 0x00 */	  //注：只有GPIO0和8有该寄存器
  __IO  uint32_t SETR;       			/*!< 端口方向设置寄存器          	Address offset: 0x04 */
  __IO  uint32_t IDR;        			/*!< 输入数据寄存器      	 		Address offset: 0x08 */
  __IO  uint32_t ODR;        			/*!< 输出数据寄存器      	 		Address offset: 0x0C */
  __IO  uint32_t PUR;       			/*!< 输入上拉控制寄存器  			Address offset: 0x10 */
  __IO  uint32_t DSR;       			/*!< 驱动能力控制寄存器  	 		Address offset: 0x14 */  
  
//  __IO  uint32_t ASACMR               /*!< 模拟引脚配置寄存器           	Address offset: 0xBC */
//  __IO  uint32_t ASIOUTR              /*!< ACM恒流输出引脚控制寄存器    	Address offset: 0xC0 */ 
  
} GPIO_TypeDef;

/**************************************Analog I/O******************************/ 

#define GPIO_ASACMR          			 *(__IO  uint32_t*)0x4000F0BC		/*!< 模拟I/O口上拉设置寄存器 */	
#define GPIO_ASIOUTR         			 *(__IO  uint32_t*)0x4000F0C0		/*!< ACM恒流输出端口设置寄存器 */	

/*******************LCD*************************/            		//LCD  Base Address:0x4001 0000
typedef struct
{
  __IO  uint32_t CPMR;     				/*!< charge pump控制寄存器          Address offset: 0x00 */
  __IO  uint32_t CR;     				/*!< LCD控制寄存器         			Address offset: 0x04 */
  __IO  uint32_t COMR;    				/*!< COM引脚属性设置寄存器         	Address offset: 0x08 */
  __IO  uint32_t SEGR1;    				/*!< SEG引脚属性设置寄存器          Address offset: 0x0C */
  __IO  uint32_t SEGR2;    				/*!< SEG引脚属性设置寄存器          Address offset: 0x10 */
  __IO  uint32_t DR0;    				/*!< 数据寄存器0            		Address offset: 0x14 */
  __IO  uint32_t DR1;    				/*!< 数据寄存器1            		Address offset: 0x18 */
  __IO  uint32_t DR2;    				/*!< 数据寄存器2            		Address offset: 0x1C */
  __IO  uint32_t DR3;    				/*!< 数据寄存器3            		Address offset: 0x20 */
  __IO  uint32_t DR4;    				/*!< 数据寄存器4            		Address offset: 0x24 */
  __IO  uint32_t DR5;    				/*!< 数据寄存器5            		Address offset: 0x28 */
  __IO  uint32_t DR6;    				/*!< 数据寄存器6            		Address offset: 0x2C */
  __IO  uint32_t DR7;    				/*!< 数据寄存器7            		Address offset: 0x30 */ 
  __IO  uint32_t DR8;    				/*!< 数据寄存器8            		Address offset: 0x34 */
  __IO  uint32_t DR9;    				/*!< 数据寄存器9            		Address offset: 0x38 */
  __IO  uint32_t DR10;    				/*!< 数据寄存器10           		Address offset: 0x3C */
  
} LCD_TypeDef;

/*********************SDADC*********************/                   //SDADC  Base Address:0x4001 1000
typedef struct
{
  __IO  uint32_t IA_CR;          		/*!< IA控制寄存器          			Address offset:0x00 */
  __IO  uint32_t SDADC_CR;   		 	/*!< SDADC控制寄存器         		Address offset:0x04 */
  __IO  uint32_t EMI_CR;         	 	/*!< EMI控制寄存器         			Address offset:0x08 */
  __IO  uint32_t SDADC_SR;    		    /*!< SDADC状态寄存器 	       	 	Address offset:0x0C */
  __IO  uint32_t SDADC_DR;              /*!< SDADC数据寄存器    			Address offset:0x10 */
  __IO  uint32_t TS_CR;                 /*!< 温度设置寄存器    			    Address offset:0x14 */
  __IO  uint32_t IA_CR2;                /*!< IA控制寄存器2          		Address offset:0x18 */
} SDADC_TypeDef;

/*********************SARADC********************/                   //SARADC  Base Address:0x4001 2000
typedef struct
{
  __IO  uint32_t CR0;        			/*!< SARADC控制寄存器0          	Address offset:0x00 */
  __IO  uint32_t CR1;    				/*!< SARADC控制寄存器1          	Address offset:0x04 */
  __IO  uint32_t CR2;        			/*!< SARADC控制寄存器2          	Address offset:0x08 */
  __IO  uint32_t CR3;    				/*!< SARADC控制寄存器3  		    Address offset:0x0C */
  __IO  uint32_t CR4;       			/*!< SARADC控制寄存器4     			Address offset:0x10 */
  __IO  uint32_t CR5;        			/*!< SARADC控制寄存器5      		Address offset:0x14 */
  __IO  uint32_t SR;       				/*!< SARADC状态寄存器 		    	Address offset:0x18 */
  __IO  uint32_t DR;        			/*!< SARADC数据寄存器           	Address offset:0x1C */

} SARADC_TypeDef;

/*********************DBG***********************/ 					//DBG  Base Address:0x4001 3000 
typedef struct
{
  __IO  uint32_t IDR;    			/*!< MCU ID码            			    Address offset: 0x00 */
  __IO  uint32_t CR; 				/*!< MCU配置寄存器            			Address offset: 0x04 */
  
} DBGMCU_TypeDef;

/********************PWR*********************/	//???????		  //PWR  Base Address:0x4001 d000
//typedef struct
//{
//  __IO  uint32_t AP_CR;        		/*!< AVDDR&ACM配置寄存器        	Address offset:0x0C */
//  __IO  uint32_t TS_CR;   			/*!< 温度传感器控制寄存器        	Address offset:0x10 */
//  __IO  uint32_t BG_CR;         		/*!< BG控制寄存器         			Address offset:0x14 */
//  __IO  uint32_t BG_CAL;        		/*!< BG校准数据寄存器          		Address offset:0x18 */
//  __IO  uint32_t SIN_CR;   			/*!< 正弦波控制寄存器         		Address offset:0x1C */
//  __IO  uint32_t OP_CR;         		/*!< 运放控制寄存器         		Address offset:0x20 */
//  __IO  uint32_t DLDO_CR;        		/*!< DVDDR输出控制寄存器          	Address offset:0x24 */
//  __IO  uint32_t IOUT_CR;   			/*!< ACM恒流输出配置寄存器         	Address offset:0x28 */
//   
//} PWR_TypeDef;
typedef struct
{
  __IO  uint32_t BG_CR;         		/*!< BG控制寄存器         			Address offset:0x00 */
  __IO  uint32_t AP_CR;        			/*!< AVDDR&ACM配置寄存器        	Address offset:0x04 */
    uint32_t RESERVED0;                 /*!< 寄存器保留                     Address offset:0x08 */
  __IO  uint32_t DLDO_CR;        		/*!< DVDDR输出控制寄存器          	Address offset:0x0C */

} PWR_TypeDef;

/*********************LBT***********************/ 					//LBT   Base Address:0x4001 e000
typedef struct
{
  __IO  uint32_t CR;    			 /*!< LBT控制寄存器            		    Address offset: 0x00 */
  __IO  uint32_t SR; 				 /*!< 状态寄存器            			Address offset: 0x04 */
  __IO  uint32_t CAPM_CR; 			 /*!< 控制寄存器            			Address offset: 0x08 */
  __IO  uint32_t CR2; 			     /*!< LBT控制寄存器 2            	    Address offset: 0x0C */
 
} LBT_TypeDef;
/*********************SIN&OP***********************/ 					 //SIN&OP   Base Address:0x4001 f000
typedef struct
{
    uint32_t RESERVED0;                 /*!< 寄存器保留                     Address offset:0x00 */
  __IO  uint32_t OP_CR;        			/*!< OP控制寄存器       	        Address offset:0x04 */

} OP_TypeDef;
/***********************RCC***********************/					//RCC  Base Address:0x4002 0000
typedef struct
{
  __IO  uint32_t IHRC_CR;    			/*!< IHRC控制寄存器           		Address offset: 0x00 */
  __IO  uint32_t ILRC_CR;   			/*!< ILRC控制寄存器           		Address offset: 0x04 */
  __IO  uint32_t XTOSC_CR;    			/*!< XTOSC控制寄存器           		Address offset: 0x08 */  
  __IO  uint32_t XTOSC_SR;    			/*!< XTOSC状态寄存器           		Address offset: 0x0C */  
  __IO  uint32_t MCLK_CFGR;    			/*!< 系统时钟配置寄存器             Address offset: 0x10 */
  __IO  uint32_t CLKOUT_CR;    			/*!< 时钟输出控制寄存器             Address offset: 0x14 */
  __IO  uint32_t IHRC_CLBR;    			/*!< IHRC校准参考寄存器             Address offset: 0x18 */
  __IO  uint32_t ILRC_CLBR;    			/*!< ILRC校准参考寄存器             Address offset: 0x1C */
  __IO  uint32_t RST_SR;    			/*!< 复位控制寄存器           		Address offset: 0x20 */
  __IO  uint32_t LVD_CR;    			/*!< 低压复位使能寄存器      		Address offset: 0x24 */
  __IO  uint32_t APB_RSTR;    			/*!< APB外设复位寄存器              Address offset: 0x28 */
  __IO  uint32_t AHB_ENR;      			/*!< 外设时钟使能寄存器             Address offset: 0x2C */
  __IO  uint32_t APB_ENR;      			/*!< 外设时钟使能寄存器             Address offset: 0x30 */ 
  __IO  uint32_t APB_CFGR1;      		/*!< 外设时钟配置寄存器1            Address offset: 0x34 */ 
  __IO  uint32_t APB_CFGR2;      		/*!< 外设时钟使能寄存器2            Address offset: 0x38 */ 

} RCC_TypeDef;

/******************FLASH************************/    				 //FLASH  Base Address:0x4002 1000
typedef struct
{
  __IO  uint32_t KEYR;    				/*!< FPEC键寄存器            		Address offset: 0x00 */
  __IO  uint32_t OPTKEYR; 				/*!< 选项字节键寄存器        		Address offset: 0x04 */
  __IO  uint32_t SR;      				/*!< 闪存状态寄存器          		Address offset: 0x08 */
  __IO  uint32_t CR; 					/*!< 闪存控制寄存器          		Address offset: 0x0C */
  __IO  uint32_t AR; 					/*!< 闪存地址寄存器          		Address offset: 0x10 */
  __IO  uint32_t OBR; 					/*!< 选项字节寄存器          		Address offset: 0x14 */  
  __IO  uint32_t WRPR; 					/*!< 写保护寄存器            		Address offset: 0x18 */
  __IO  uint32_t ACR; 					/*!< 闪存访问控制寄存器            	Address offset: 0x1C */  

} FLASH_TypeDef;

/******************FLASH_OB************************/    			//FLASH  Base Address:0x1FFF 8200
typedef struct
{
  __IO  uint16_t RDP;    				/*!< FPEC键寄存器            		Address offset: 0x00 */
  __IO  uint16_t USER; 				    /*!< 选项字节键寄存器        		Address offset: 0x02 */
  __IO  uint16_t WRP0;      			/*!< 闪存状态寄存器          	    Address offset: 0x04 */
  __IO  uint16_t WRP1; 					/*!< 闪存控制寄存器          		Address offset: 0x06 */
  __IO  uint16_t WRP2; 					/*!< 闪存地址寄存器          		Address offset: 0x08 */
  __IO  uint16_t WRP3; 					/*!< 选项字节寄存器          		Address offset: 0x0A */   

} OB_TypeDef;

 /******************SysTick********************/      				//CORE TM  Base Address:0xE000 E010

typedef struct
{
  __IO   uint32_t  CSR;             	/*!< 控制状态寄存器       			Address offset: 0x00 */
  __IO   uint32_t  RVR;             	/*!< 重载值寄存器          			Address offset: 0x04 */
  __IO   uint32_t  CVR;             	/*!< 当前值寄存器          			Address offset: 0x08 */
  __IO   uint32_t  CALIBR;           	/*!< 校准寄存器            			Address offset: 0x0C */
  
} SysTick_TypeDef;

/**************************************Interrupt*********************************/  //嵌套中断向量列表控制器
 
#define VIC_ISER             			 *(__IO  uint32_t*)0xE000E100      	/*!< 中断使能设置寄存器 */
#define VIC_IWER             			 *(__IO  uint32_t*)0xE000E140      	/*!< 低功耗唤醒设置寄存器 */
#define VIC_ICER             			 *(__IO  uint32_t*)0xE000E180      	/*!< 中断使能清除寄存器 */
#define VIC_IWDR             			 *(__IO  uint32_t*)0xE000E1C0      	/*!< 低功耗唤醒清除寄存器 */

#define VIC_ISPR             			 *(__IO  uint32_t*)0xE000E200      	/*!< 中断挂起设置寄存器 */
#define VIC_ICPR             			 *(__IO  uint32_t*)0xE000E280      	/*!< 中断挂起清除寄存器 */
#define VIC_IABR             			 *(__IO  uint32_t*)0xE000E300      	/*!< 中断响应状态寄存器 */

#define VIC_IPR0             			 *(__IO  uint32_t*)0xE000E400      	/*!< 中断优先级设置寄存器0 */
#define VIC_IPR1             			 *(__IO  uint32_t*)0xE000E404      	/*!< 中断优先级设置寄存器1 */
#define VIC_IPR2             			 *(__IO  uint32_t*)0xE000E408      	/*!< 中断优先级设置寄存器2 */
#define VIC_IPR3             			 *(__IO  uint32_t*)0xE000E40C      	/*!< 中断优先级设置寄存器3 */   
#define VIC_IPR4             			 *(__IO  uint32_t*)0xE000E410      	/*!< 中断优先级设置寄存器4 */
#define VIC_IPR5             			 *(__IO  uint32_t*)0xE000E414      	/*!< 中断优先级设置寄存器5 */
#define VIC_IPR6             			 *(__IO  uint32_t*)0xE000E418      	/*!< 中断优先级设置寄存器6 */
#define VIC_IPR7             			 *(__IO  uint32_t*)0xE000E41C      	/*!< 中断优先级设置寄存器7 */

#define VIC_ISR              			 *(__IO  uint32_t*)0xE000EC00      	/*!< 中断状态寄存器 */
#define VIC_IPTR             			 *(__IO  uint32_t*)0xE000EC04      	/*!< 中断优先级阈值寄存器 */

/**************************************BIST I/0**********************************/     //公司内部测试用  			

#define BIST_KEY             			 *(__IO  uint32_t*)0x500007C8
#define BIST_STA             			 *(__IO  uint32_t*)0x5000033C

/************************************* 模拟IO***********************************/			
//#define GPIO_ASACMR          			 *(__IO  uint32_t*)0x4000F0BC
//#define GPIO_ASIOUTR         			 *(__IO  uint32_t*)0x4000F0C0

/****************************add to group Peripheral_memory_map******************/

#define CORE_BASE              			((uint32_t)0x00000000) 				/*!< CORE base address in the alias region */
#define FLASH_BASE              		((uint32_t)0x08000000) 				/*!< FLASH base address in the alias region */

#define SRAM_BASE              			((uint32_t)0x20000000) 				/*!< SRAM base address in the alias region */
#define PERIPH_BASE            			((uint32_t)0x40000000) 				/*!< Peripheral base address in the alias region */

/********************************* Peripherals memory  map **********************/
#define EXINT_BASE            			(PERIPH_BASE+0x00000000)							/*!< 外部中断寄存器 */		
#define TM0_BASE              			(PERIPH_BASE+0x00001000)                			/*!< 定时器0寄存器 */	
#define TM1_BASE              			(PERIPH_BASE+0x00002000)							/*!< 定时器1寄存器 */
#define TM2_BASE              			(PERIPH_BASE+0x00003000)							/*!< 定时器2寄存器 */	
#define RTC_BASE              			(PERIPH_BASE+0x00004000)							/*!< RTC寄存器 */	
#define IWDG_BASE             			(PERIPH_BASE+0x00005000)							/*!< 独立看门狗寄存器 */
#define WWDG_BASE             			(PERIPH_BASE+0x00006000)							/*!< 窗口看门狗寄存器 */	
#define PWM0_BASE             			(PERIPH_BASE+0x00007000)							/*!< PWM_PDM0寄存器 */
#define PWM1_BASE             			(PERIPH_BASE+0x00008000)							/*!< PWM_PDM1寄存器 */
#define BUZZER0_BASE             		(PERIPH_BASE+0x00009000)							/*!< 蜂鸣器0寄存器 */
#define BUZZER1_BASE          	  		(PERIPH_BASE+0x0000A000)							/*!< 蜂鸣器1寄存器 */
#define I2C_BASE              			(PERIPH_BASE+0x0000B000)							/*!< I2C寄存器 */	
#define SPI_BASE              			(PERIPH_BASE+0x0000C000)							/*!< SPI寄存器 */
#define UART0_BASE            			(PERIPH_BASE+0x0000D000)							/*!< UART0寄存器 */
#define UART1_BASE            			(PERIPH_BASE+0x0000E000)							/*!< UART1寄存器 */

/**************************************	GPIO ***********************************/			
#define GPIO0_BASE            			(PERIPH_BASE+0x0000F000)							/*!< PT0寄存器 */
#define GPIO1_BASE            			(PERIPH_BASE+0x0000F014)							/*!< PT1寄存器 */	
#define GPIO2_BASE            			(PERIPH_BASE+0x0000F028)							/*!< PT2寄存器 */	
#define GPIO3_BASE            			(PERIPH_BASE+0x0000F03C)							/*!< PT3寄存器 */
#define GPIO4_BASE            			(PERIPH_BASE+0x0000F050)							/*!< PT4寄存器 */
#define GPIO5_BASE            			(PERIPH_BASE+0x0000F064)							/*!< PT5寄存器 */
#define GPIO6_BASE            			(PERIPH_BASE+0x0000F078)							/*!< PT6寄存器 */
#define GPIO7_BASE            			(PERIPH_BASE+0x0000F08C)							/*!< PT7寄存器 */
#define GPIO8_BASE            			(PERIPH_BASE+0x0000F0A4)							/*!< PT8寄存器 */


/**************************************	LCD ************************************/
#define LCD_BASE              			(PERIPH_BASE+0x00010000)							/*!< LCD寄存器 */
	

/**************************************	ADC ************************************/
#define SDADC_BASE              		(PERIPH_BASE+0x00011000)							/*!< ∑-∆ ADC/SDADC寄存器 */
#define SARADC_BASE           			(PERIPH_BASE+0x00012000)							/*!< SAR ADC寄存器 */


/**************************************	SWD ************************************/
#define DBGMCU_BASE              		(PERIPH_BASE+0x00013000)							/*!< SWD调试寄存器 */

/**************************************	BG ************************************/
#define PWR_BASE              			(PERIPH_BASE+0x0001D000)

/**************************************	LBT ************************************/
#define LBT_BASE                        (PERIPH_BASE+0x0001E000)

/**************************************	SIN&OP ************************************/
#define OP_BASE						    (PERIPH_BASE+0x0001F000)

/**************************************	RCC ************************************/
#define RCC_BASE              			(PERIPH_BASE+0x00020000)						/*!< 时钟和复位寄存器 */


/********************************* FLASH Interface  ****************************/
#define FLASH_INTERFACE_BASE            (PERIPH_BASE+0x00021000)                       	/*!< 闪存存储器接口寄存器 */       
#define FLASH_OB_BASE            		((uint32_t)0x1FFF8200)                          /*选项字节编程寄存器*/

/********************************* SysTick ************************/
#define SysTick_BASE            		((uint32_t)0xE000E010)   						/*!< 系统计数器 */

/* add to group Peripheral_declaration */

#define EXINT            				((EXINT_TypeDef *) EXINT_BASE  )
#define TM0             				((TM_TypeDef   *) TM0_BASE    )              
#define TM1             				((TM_TypeDef   *) TM1_BASE    )
#define TM2             				((TM_TypeDef   *) TM2_BASE    )
#define RTC              				((RTC_TypeDef   *) RTC_BASE    )
#define IWDG             				((IWDG_TypeDef  *) IWDG_BASE   )
#define WWDG             				((WWDG_TypeDef  *) WWDG_BASE   )
#define PWM0             				((PWM_TypeDef   *) PWM0_BASE   )
#define PWM1             				((PWM_TypeDef   *) PWM1_BASE   )
#define BUZ0             				((BUZ_TypeDef   *) BUZZER0_BASE )
#define BUZ1             				((BUZ_TypeDef   *) BUZZER1_BASE )
#define I2C              				((I2C_TypeDef   *) I2C_BASE    )
#define SPI              				((SPI_TypeDef   *) SPI_BASE    )
#define UART0            				((UART_TypeDef  *) UART0_BASE  )
#define UART1            				((UART_TypeDef  *) UART1_BASE  )
#define GPIO0            				((GPIO_TypeDef  *) GPIO0_BASE  )
#define GPIO1            				((GPIO_TypeDef  *) GPIO1_BASE  )
#define GPIO2            				((GPIO_TypeDef  *) GPIO2_BASE  )
#define GPIO3            				((GPIO_TypeDef  *) GPIO3_BASE  )
#define GPIO4            				((GPIO_TypeDef  *) GPIO4_BASE  )
#define GPIO5            				((GPIO_TypeDef  *) GPIO5_BASE  )
#define GPIO6            				((GPIO_TypeDef  *) GPIO6_BASE  )
#define GPIO7            				((GPIO_TypeDef  *) GPIO7_BASE  )
#define GPIO8            				((GPIO_TypeDef  *) GPIO8_BASE  )
#define LCD              				((LCD_TypeDef   *) LCD_BASE    )
#define SDADC              				((SDADC_TypeDef *) SDADC_BASE  )
#define SARADC           				((SARADC_TypeDef*) SARADC_BASE )
#define DBGMCU              			((DBGMCU_TypeDef  *) DBGMCU_BASE )
#define LBT              				((LBT_TypeDef   *)  LBT_BASE   )
#define PWR           				    ((PWR_TypeDef*) PWR_BASE )  
#define OP           				    ((OP_TypeDef*) OP_BASE )
#define RCC              				((RCC_TypeDef   *) RCC_BASE    )
#define FLASH            				((FLASH_TypeDef *) FLASH_INTERFACE_BASE )
#define OB                              ((OB_TypeDef *) FLASH_OB_BASE )
#define SysTick          				((SysTick_TypeDef *) SysTick_BASE  )

/**********************************PWR*************************************/

/********* Bits definition for TS_CR register **********/							//TS_CR寄存器	
 //#define TS_CR_BGEN                 	((uint8_t)0x01)
 #define TS_CR_TSOEN           			((uint8_t)0x02)
 #define TS_CR_TSEL            			((uint8_t)0x04)
 #define TS_CR_TCPEN          			((uint8_t)0x08)
 #define TS_CR_TVBS             		((uint8_t)0x10)
 #define TS_CR_TCK              		((uint8_t)0x20)

/********* Bits definition for BG_CR register **********/							//BG_CR寄存器
 #define BG_CR_BGEN                 	((uint16_t)0x8000)
 
/********* Bits definition for AP_CR register **********/							//AP_CR寄存器
 #define AP_CR_AVDDREN                 	((uint32_t)0x00000001)
 
 #define AP_CR_AVDDRX                 	((uint32_t)0x0000000E)
 #define AP_CR_AVDDRX_0                 ((uint32_t)0x00000002)
 #define AP_CR_AVDDRX_1                 ((uint32_t)0x00000004)
 #define AP_CR_AVDDRX_2                 ((uint32_t)0x00000008)
 
 #define AP_CR_AVDDR_IBLEEDEN           ((uint32_t)0x00000010)
 
 #define AP_CR_ACMEN           			((uint32_t)0x00010000) 
 #define AP_CR_ACMPS           			((uint32_t)0x00060000) 
 #define AP_CR_ACMPS_0           		((uint32_t)0x00020000)
 #define AP_CR_ACMPS_1           		((uint32_t)0x00040000)
 
 /********* Bits definition for DLDO_CR register **********/							//DLDO_CR寄存器
 #define DLDO_CR_DLDO_SOFTSTART_BYP     ((uint32_t)0x00100000)
 #define DLDO_CR_DLDO_EXTCAPSEL         ((uint32_t)0x00080000)
 #define DLDO_CR_DLDO_IBLEEDEN          ((uint32_t)0x00040000)
 
 
 #define DLDO_CR_DVDDRX                 ((uint8_t)0x07)
 #define DLDO_CR_DVDDRX_0               ((uint8_t)0x01)
 #define DLDO_CR_DVDDRX_1               ((uint8_t)0x02)
 #define DLDO_CR_DVDDRX_2               ((uint8_t)0x04)

 /******** Bits definition for LBT_CR register **********/							//LBT_CR寄存器
 #define LBT_CR_COMPX     				((uint32_t)0x00000007)
 #define LBT_CR_COMPX_0     			((uint32_t)0x00000001)
 #define LBT_CR_COMPX_1     			((uint32_t)0x00000002)
 #define LBT_CR_COMPX_2     			((uint32_t)0x00000004)
 
 #define LBT_CR_COMPEN     				((uint32_t)0x00000008)
 #define LBT_CR_LBTO    				((uint32_t)0x00000010)
 #define LBT_CR_DELAYEN     			((uint32_t)0x00000020)
 #define LBT_CR_LBTINSEL    			((uint32_t)0x00000040) 
 #define LBT_CR_LBTIE    				((uint32_t)0x00008000)

 #define LBT_CR_DAP    				    ((uint32_t)0x0F000000)
 #define LBT_CR_DAP_0    				((uint32_t)0x01000000)
 #define LBT_CR_DAP_1    				((uint32_t)0x02000000)
 #define LBT_CR_DAP_2    				((uint32_t)0x04000000)
 #define LBT_CR_DAP_3    				((uint32_t)0x08000000)
 
 #define LBT_CR_DAN    				    ((uint32_t)0x70000000)
 #define LBT_CR_DAN_0    				((uint32_t)0x10000000)
 #define LBT_CR_DAN_1    				((uint32_t)0x20000000)
 #define LBT_CR_DAN_2    				((uint32_t)0x40000000) 
 #define LBT_CR_DAEN    				((uint32_t)0x80000000) 

/******** Bits definition for LBT_SR register **********/							//LBT_SR寄存器
 #define LBT_SR_LBTIF    				((uint8_t)0x01) 
 
/******** Bits definition for CAPM_CR register *********/							//CAPM_CR寄存器	
 #define CAPM_CR_CAPMEN    				((uint8_t)0x01) 
 #define CAPM_CR_CAMPS    				((uint8_t)0x0E) 
 #define CAPM_CR_CAPMS_0   				((uint8_t)0x02) 
 #define CAPM_CR_CAPMS_1    			((uint8_t)0x04) 
 #define CAPM_CR_CAPMS_2    			((uint8_t)0x08) 
 
/******** Bits definition for LBT_CR2 register **********/							//LBT_SR寄存器
 #define LBT_CR2_AUD_OEN    			((uint32_t)0x00020000) 
 #define LBT_CR2_DAO_OEN    			((uint32_t)0x00010000) 
 
 

/********* Bits definition for OP_CR register **********/							//OP_CR寄存器
 #define OP_CR_OPAEN                  	((uint32_t)0x00000001)
 #define OP_CR_OPACS           			((uint32_t)0x00000002) 
 
 #define OP_CR_OPANS           			((uint32_t)0x0000000C)
 #define OP_CR_OPANS_0           		((uint32_t)0x00000004)
 #define OP_CR_OPANS_1           		((uint32_t)0x00000008)
 #define OP_CR_OPAPS           			((uint32_t)0x00000030)
 #define OP_CR_OPAPS_0           		((uint32_t)0x00000010)
 #define OP_CR_OPAPS_1           		((uint32_t)0x00000020)
 
 #define OP_CR_VGSW           		    ((uint32_t)0x00008000)
 
 #define OP_CR_OPAOUTS0                 ((uint32_t)0x00000040)
 #define OP_CR_OPAOUTS1           		((uint32_t)0x00000080)
 #define OP_CR_OPAOUTS2                 ((uint32_t)0x00000100)
 #define OP_CR_OPAOUTS3           		((uint32_t)0x00000200)
  
 #define OP_CR_OPBEN                 	((uint32_t)0x00010000)
 #define OP_CR_OPBCS          			((uint32_t)0x00020000)
 
 #define OP_CR_OPBNS           			((uint32_t)0x000C0000)
 #define OP_CR_OPBNS_0           		((uint32_t)0x00040000)
 #define OP_CR_OPBNS_1           		((uint32_t)0x00080000)
 #define OP_CR_OPBPS           			((uint32_t)0x00300000)
 #define OP_CR_OPBPS_0           		((uint32_t)0x00100000)
 #define OP_CR_OPBPS_1           		((uint32_t)0x00200000)
 
/********************************RCC*******************************************/

/******* Bits definition for IHRC_CR register***********/  							//IHRC控制寄存器					
#define IHRC_CR_IHRCT                	((uint32_t)0x000000FF)                      /*!< IHRCT[7:0] bits (IHRC CALIBRATION VALUE) */
#define IHRC_CR_IHRCT_0                	((uint32_t)0x00000001)
#define IHRC_CR_IHRCT_1               	((uint32_t)0x00000002)
#define IHRC_CR_IHRCT_2                	((uint32_t)0x00000004)
#define IHRC_CR_IHRCT_3               	((uint32_t)0x00000008)
#define IHRC_CR_IHRCT_4                	((uint32_t)0x00000010)
#define IHRC_CR_IHRCT_5                	((uint32_t)0x00000020)
#define IHRC_CR_IHRCT_6               	((uint32_t)0x00000040)
#define IHRC_CR_IHRCT_7                	((uint32_t)0x00000080)
#define IHRC_CR_IHRC_CPEN               ((uint32_t)0x00008000)
#define IHRC_CR_IHRCEN                  ((uint32_t)0x00010000)
#define IHRC_CR_IHRCOK                  ((uint32_t)0x00040000)

/******* Bits definition for ILRC_CR register***********/ 							//ILRC控制寄存器

#define ILRC_CR_ILRCT                	((uint32_t)0x0000001F) 
#define ILRC_CR_ILRCT_0                	((uint32_t)0x00000001)
#define ILRC_CR_ILRCT_1                	((uint32_t)0x00000002)
#define ILRC_CR_ILRCT_2                	((uint32_t)0x00000004)
#define ILRC_CR_ILRCT_3                	((uint32_t)0x00000008)
#define ILRC_CR_ILRCT_4                	((uint32_t)0x00000010)
#define ILRC_CR_ILRCEN                  ((uint32_t)0x00010000)

/******* Bits definition for XTOSC_CR register**********/ 							//XTOSC控制寄存器
  
#define XTOSC_CR_XT1CS               	((uint32_t)0x0000000F)
#define XTOSC_CR_XT1CS_0               	((uint32_t)0x00000001)
#define XTOSC_CR_XT1CS_1               	((uint32_t)0x00000002)
#define XTOSC_CR_XT1CS_2               	((uint32_t)0x00000004)
#define XTOSC_CR_XT1CS_3               	((uint32_t)0x00000008)
#define XTOSC_RES_EN                    ((uint32_t)0x00000100)
#define XTOSC_CR_XT1STPIE               ((uint32_t)0x00000200)
#define XTOSC_CR_ST1RD                  ((uint32_t)0x00000800)

#define XTOSC_CR_ST1EN              	((uint32_t)0x00001000)
#define XTOSC_CR_XTOSC1EN               ((uint32_t)0x00008000)

#ifdef SD93F115B_D 
#define XTOSC_CR_XT2CS               	((uint32_t)0x000F0000)
#define XTOSC_CR_XT2CS_0               	((uint32_t)0x00010000)
#define XTOSC_CR_XT2CS_1               	((uint32_t)0x00020000)
#define XTOSC_CR_XT2CS_2               	((uint32_t)0x00040000)
#define XTOSC_CR_XT2CS_3               	((uint32_t)0x00080000)

#define XTOSC_CR_XT2STPIE               ((uint32_t)0x02000000)
#define XTOSC_CR_ST2RD                	((uint32_t)0x08000000)
#define XTOSC_CR_ST2EN                  ((uint32_t)0x10000000)
#define XTOSC_CR_XTOSC2EN               ((uint32_t)0x80000010)
#endif
#ifdef SD93F115B_JQS 
#define XTOSC_CR_XT2CS               	((uint32_t)0x000F0000)
#define XTOSC_CR_XT2CS_0               	((uint32_t)0x00010000)
#define XTOSC_CR_XT2CS_1               	((uint32_t)0x00020000)
#define XTOSC_CR_XT2CS_2               	((uint32_t)0x00040000)
#define XTOSC_CR_XT2CS_3               	((uint32_t)0x00080000)

#define XTOSC_CR_XT2STPIE               ((uint32_t)0x02000000)
#define XTOSC_CR_ST2RD                	((uint32_t)0x08000000)
#define XTOSC_CR_ST2EN                  ((uint32_t)0x10000000)
#define XTOSC_CR_XTOSC2EN               ((uint32_t)0x80000010)
#endif
/******* Bits definition for XTOSC_SR register**********/  							//XTOSC状态寄存器
#define XTOSC_SR_XT1STPIF               ((uint8_t)0x00000001)
#define XTOSC_SR_XT2STPIF               ((uint8_t)0x00000002)

/******* Bits definition for MCLK_CFGR register*********/							//MCLK系统时钟配置寄存器
#define MCLK_CFGR_SW               		((uint32_t)0x00000001)

#define MCLK_CFGR_SYSPRE             	((uint32_t)0x0000000C)
#define MCLK_CFGR_SYSPRE_0             	((uint32_t)0x00000004)
#define MCLK_CFGR_SYSPRE_1             	((uint32_t)0x00000008)

#define MCLK_CFGR_SRCSEL            	((uint32_t)0x000000E0)
#define MCLK_CFGR_SRCSEL_0            	((uint32_t)0x00000020)
#define MCLK_CFGR_SRCSEL_1            	((uint32_t)0x00000040)
#define MCLK_CFGR_SRCSEL_2           	((uint32_t)0x00000080)

#define MCLK_CFGR_HSWIF               	((uint32_t)0x00010000)
//#define MCLK_CFGR_FLASH_LPEN            ((uint32_t)0x00020000)

/******* Bits definition for CLKOUT_CR register*********/							//CLKOUT时钟输出控制寄存器
#define CLKOUT_CR_CLKOUTS           	((uint8_t)0x07)
#define CLKOUT_CR_CLKOUTS_0           	((uint8_t)0x01)
#define CLKOUT_CR_CLKOUTS_1            	((uint8_t)0x02)
#define CLKOUT_CR_CLKOUTS_2           	((uint8_t)0x04)

#define CLKOUT_CR_CLKOUTEN              ((uint8_t)0x08)

/******* Bits definition for RST_SR register************/							//RST复位标志/状态寄存器
#define RST_SR_POR_RSTF            		((uint32_t)0x00000001)
#define RST_SR_WWDG_RSTF            	((uint32_t)0x00000002)
#define RST_SR_IWDG_RSTF            	((uint32_t)0x00000004)
#define RST_SR_SFT_RSTF              	((uint32_t)0x00000008)
#define RST_SR_PIN_RSTF            		((uint32_t)0x00000010)
#define RST_SR_OBL_RSTF            		((uint32_t)0x00000040)
#define RST_SR_BOR_RSTF            		((uint32_t)0x00000080)
#define RST_SR_RMVF              		((uint32_t)0x00008000)
#define RST_SR_RST_ERR              	((uint32_t)0x00010000)

/******* Bits definition for LVD_CR register************/							//LVD低压复位使能寄存器
#define LVD_CR_LVDEN                    ((uint8_t)0x00000001)

/******* Bits definition for APB_RSTR register**********/							//APB外设复位寄存器
#define APB_RSTR_INT_KEY                ((uint32_t)0x00000001)
#define APB_RSTR_TM0                    ((uint32_t)0x00000002)
#define APB_RSTR_TM1                    ((uint32_t)0x00000004)
#define APB_RSTR_TM2                    ((uint32_t)0x00000008)
#define APB_RSTR_RTC                    ((uint32_t)0x00000010)
#define APB_RSTR_WWDG                   ((uint32_t)0x00000040)
#define APB_RSTR_PWM0                   ((uint32_t)0x00000080)
#define APB_RSTR_PWM1                   ((uint32_t)0x00000100)
#define APB_RSTR_BUZ0                   ((uint32_t)0x00000200)
#define APB_RSTR_BUZ1                   ((uint32_t)0x00000400)
#define APB_RSTR_I2C                    ((uint32_t)0x00000800)
#define APB_RSTR_SPI                    ((uint32_t)0x00001000)
#define APB_RSTR_UART0                  ((uint32_t)0x00002000)
#define APB_RSTR_UART1                  ((uint32_t)0x00004000)
#define APB_RSTR_GPIO                   ((uint32_t)0x00008000)
#define APB_RSTR_LCD_RST                ((uint32_t)0x00010000)
#define APB_RSTR_SDADC_RST              ((uint32_t)0x00020000)
#define APB_RSTR_SARADC_RST             ((uint32_t)0x00040000)
//#define APB_RSTR_PWR_RST                ((uint32_t)0x00080000)

/******* Bits definition for APB_ENR register***********/							//APB外设时钟使能寄存器
#define APB_ENR_INT_KEY_CKEN            ((uint32_t)0x00000001)
#define APB_ENR_TM0_CKEN                ((uint32_t)0x00000002)
#define APB_ENR_TM1_CKEN                ((uint32_t)0x00000004)
#define APB_ENR_TM2_CKEN                ((uint32_t)0x00000008)

#define APB_ENR_RTC_CKEN                ((uint32_t)0x00000010)
#define APB_ENR_WWDG_CKEN               ((uint32_t)0x00000040)
#define APB_ENR_PWM0_CKEN               ((uint32_t)0x00000080)

#define APB_ENR_PWM1_CKEN               ((uint32_t)0x00000100)
#define APB_ENR_BUZ0_CKEN               ((uint32_t)0x00000200)
#define APB_ENR_BUZ1_CKEN               ((uint32_t)0x00000400)
#define APB_ENR_I2C_CKEN                ((uint32_t)0x00000800)

#define APB_ENR_SPI_CKEN                ((uint32_t)0x00001000)
#define APB_ENR_UART0_CKEN              ((uint32_t)0x00002000)
#define APB_ENR_UART1_CKEN              ((uint32_t)0x00004000)
#define APB_ENR_GPIO_CKEN               ((uint32_t)0x00008000)

#define APB_ENR_LCD_CKEN                ((uint32_t)0x00010000)
#define APB_ENR_SDADC_CKEN              ((uint32_t)0x00020000)
#define APB_ENR_SARADC_CKEN             ((uint32_t)0x00040000)
//#define APB_ENR_PWR_CKEN             	((uint32_t)0x00080000)

/******* Bits definition for APB_CFGR1 register*********/							//APB外设时钟配置寄存器1

#define APB_CFGR1_T0CD              	((uint32_t)0x00000007)
#define APB_CFGR1_T0CD_0             	((uint32_t)0x00000001)
#define APB_CFGR1_T0CD_1             	((uint32_t)0x00000002)
#define APB_CFGR1_T0CD_2             	((uint32_t)0x00000004)

#define APB_CFGR1_T0CKS             	((uint32_t)0x00000070)
#define APB_CFGR1_T0CKS_0            	((uint32_t)0x00000010)
#define APB_CFGR1_T0CKS_1            	((uint32_t)0x00000020)
#define APB_CFGR1_T0CKS_2            	((uint32_t)0x00000040)

#define APB_CFGR1_T1CD              	((uint32_t)0x00000700)
#define APB_CFGR1_T1CD_0             	((uint32_t)0x00000100)
#define APB_CFGR1_T1CD_1             	((uint32_t)0x00000200)
#define APB_CFGR1_T1CD_2             	((uint32_t)0x00000400)

#define APB_CFGR1_T1CKS             	((uint32_t)0x00003000)
#define APB_CFGR1_T1CKS_0            	((uint32_t)0x00001000)
#define APB_CFGR1_T1CKS_1            	((uint32_t)0x00002000)

#define APB_CFGR1_T2CD              	((uint32_t)0x00030000)
#define APB_CFGR1_T2CD_0             	((uint32_t)0x00010000)
#define APB_CFGR1_T2CD_1             	((uint32_t)0x00020000)

#define APB_CFGR1_T2CKS             	((uint32_t)0x00300000)
#define APB_CFGR1_T2CKS_0            	((uint32_t)0x00100000)
#define APB_CFGR1_T2CKS_1            	((uint32_t)0x00200000)

/******* Bits definition for APB_CFGR2 register*********/							//APB外设时钟配置寄存器2
#define APB_CFGR2_PWM0CD             	((uint32_t)0x00000003)
#define APB_CFGR2_PWM0CD_0            	((uint32_t)0x00000001)
#define APB_CFGR2_PWM0CD_1            	((uint32_t)0x00000002)

#define APB_CFGR2_PWM0CKS            	((uint32_t)0x0000000C)
#define APB_CFGR2_PWM0CKS_0           	((uint32_t)0x00000004)
#define APB_CFGR2_PWM0CKS_1           	((uint32_t)0x00000008)

#define APB_CFGR2_PWM1CD             	((uint32_t)0x00000030)
#define APB_CFGR2_PWM1CD_0            	((uint32_t)0x00000010)
#define APB_CFGR2_PWM1CD_1            	((uint32_t)0x00000020)

#define APB_CFGR2_PWM1CKS            	((uint32_t)0x000000C0)
#define APB_CFGR2_PWM1CKS_0           	((uint32_t)0x00000040)
#define APB_CFGR2_PWM1CKS_1           	((uint32_t)0x00000080)

#define APB_CFGR2_BUZ0CKS            	((uint32_t)0x00000100)
#define APB_CFGR2_BUZ1CKS               ((uint32_t)0x00000400)

#define APB_CFGR2_RTCCKS            	((uint32_t)0x00003000)
#define APB_CFGR2_RTCCKS_0           	((uint32_t)0x00001000)
#define APB_CFGR2_RTCCKS_1           	((uint32_t)0x00002000)

#define APB_CFGR2_I2CCD           	((uint32_t)0x00030000
#define APB_CFGR2_I2CCD_0          	((uint32_t)0x00010000)
#define APB_CFGR2_I2CCD_1         	((uint32_t)0x00020000)
	
#define APB_CFGR2_U0CKS             	((uint32_t)0x00300000)
#define APB_CFGR2_U0CKS_0            	((uint32_t)0x00100000)
#define APB_CFGR2_U0CKS_1            	((uint32_t)0x00200000)

#define APB_CFGR2_U1CKS             	((uint32_t)0x03000000)
#define APB_CFGR2_U1CKS_0            	((uint32_t)0x01000000)
#define APB_CFGR2_U1CKS_1            	((uint32_t)0x02000000)

/******* Bits definition for AHB_ENR register***********/							//AHB外设时钟使能寄存器
#define AHB_ENR_SRAMEN                	((uint32_t)0x00000001)
#define AHB_ENR_FLITFEN                 ((uint32_t)0x00000002)
/********************************VIC*******************************************/

/******* Bits definition for VIC_ISER register**********/
 #define VIC_ISER_0                 	((uint32_t)0x00000001)						//中断使能通道0
 #define VIC_ISER_1                		((uint32_t)0x00000002)
 #define VIC_ISER_2                 	((uint32_t)0x00000004)
 #define VIC_ISER_3                 	((uint32_t)0x00000008)
 #define VIC_ISER_4                 	((uint32_t)0x00000010)
 #define VIC_ISER_5                		((uint32_t)0x00000020)
 #define VIC_ISER_6                 	((uint32_t)0x00000040)
 #define VIC_ISER_7                 	((uint32_t)0x00000080)
 
 #define VIC_ISER_8                 	((uint32_t)0x00000100)
 #define VIC_ISER_9                		((uint32_t)0x00000200)
 #define VIC_ISER_10                 	((uint32_t)0x00000400)
 #define VIC_ISER_11                 	((uint32_t)0x00000800)
 #define VIC_ISER_12                 	((uint32_t)0x00001000)
 #define VIC_ISER_13                 	((uint32_t)0x00002000)
 #define VIC_ISER_14                 	((uint32_t)0x00004000)
 #define VIC_ISER_15                 	((uint32_t)0x00008000)

 #define VIC_ISER_16                 	((uint32_t)0x00010000)
 #define VIC_ISER_17                 	((uint32_t)0x00020000)
 #define VIC_ISER_18                 	((uint32_t)0x00040000)
 #define VIC_ISER_19                 	((uint32_t)0x00080000)
 #define VIC_ISER_20                 	((uint32_t)0x00100000)
 #define VIC_ISER_21                 	((uint32_t)0x00200000) 						//中断使能通道21 

/******* Bits definition for VIC_ICER register**********/
 #define VIC_ICER_0                 	((uint32_t)0x00000001)						//中断清除通道0
 #define VIC_ICER_1                		((uint32_t)0x00000002)
 #define VIC_ICER_2                 	((uint32_t)0x00000004)
 #define VIC_ICER_3                 	((uint32_t)0x00000008)
 #define VIC_ICER_4                 	((uint32_t)0x00000010)
 #define VIC_ICER_5                		((uint32_t)0x00000020)
 #define VIC_ICER_6                 	((uint32_t)0x00000040)
 #define VIC_ICER_7                 	((uint32_t)0x00000080)
 
 #define VIC_ICER_8                 	((uint32_t)0x00000100)
 #define VIC_ICER_9                		((uint32_t)0x00000200)
 #define VIC_ICER_10                 	((uint32_t)0x00000400)
 #define VIC_ICER_11                 	((uint32_t)0x00000800)
 #define VIC_ICER_12                 	((uint32_t)0x00001000)
 #define VIC_ICER_13                 	((uint32_t)0x00002000)
 #define VIC_ICER_14                 	((uint32_t)0x00004000)
 #define VIC_ICER_15                 	((uint32_t)0x00008000)

 #define VIC_ICER_16                 	((uint32_t)0x00010000)
 #define VIC_ICER_17                 	((uint32_t)0x00020000)
 #define VIC_ICER_18                 	((uint32_t)0x00040000)
 #define VIC_ICER_19                 	((uint32_t)0x00080000)
 #define VIC_ICER_20                 	((uint32_t)0x00100000)
 #define VIC_ICER_21                 	((uint32_t)0x00200000) 					 	//中断清除通道21

/******* Bits definition for VIC_IWER register**********/
 #define VIC_IWER_0                 	((uint32_t)0x00000001)						//低功耗唤醒通道0
 #define VIC_IWER_1                		((uint32_t)0x00000002)
 #define VIC_IWER_2                 	((uint32_t)0x00000004)
 #define VIC_IWER_3                 	((uint32_t)0x00000008)
 #define VIC_IWER_4                 	((uint32_t)0x00000010)
 #define VIC_IWER_5                		((uint32_t)0x00000020)
 #define VIC_IWER_6                 	((uint32_t)0x00000040)
 #define VIC_IWER_7                 	((uint32_t)0x00000080)
 
 #define VIC_IWER_8                 	((uint32_t)0x00000100)
 #define VIC_IWER_9                		((uint32_t)0x00000200)
 #define VIC_IWER_10                 	((uint32_t)0x00000400)
 #define VIC_IWER_11                 	((uint32_t)0x00000800)
 #define VIC_IWER_12                 	((uint32_t)0x00001000)
 #define VIC_IWER_13                 	((uint32_t)0x00002000)
 #define VIC_IWER_14                 	((uint32_t)0x00004000)
 #define VIC_IWER_15                 	((uint32_t)0x00008000)

 #define VIC_IWER_16                 	((uint32_t)0x00010000)
 #define VIC_IWER_17                 	((uint32_t)0x00020000)
 #define VIC_IWER_18                 	((uint32_t)0x00040000)
 #define VIC_IWER_19                 	((uint32_t)0x00080000)
 #define VIC_IWER_20                 	((uint32_t)0x00100000)
 #define VIC_IWER_21                 	((uint32_t)0x00200000)						//低功耗唤醒通道21

/******* Bits definition for VIC_IWDR register**********/
 #define VIC_IWDR_0                 	((uint32_t)0x00000001)						//低功耗唤醒清除通道0
 #define VIC_IWDR_1                		((uint32_t)0x00000002)
 #define VIC_IWDR_2                 	((uint32_t)0x00000004)
 #define VIC_IWDR_3                 	((uint32_t)0x00000008)
 #define VIC_IWDR_4                 	((uint32_t)0x00000010)
 #define VIC_IWDR_5                		((uint32_t)0x00000020)
 #define VIC_IWDR_6                 	((uint32_t)0x00000040)
 #define VIC_IWDR_7                 	((uint32_t)0x00000080)
 
 #define VIC_IWDR_8                 	((uint32_t)0x00000100)
 #define VIC_IWDR_9                		((uint32_t)0x00000200)
 #define VIC_IWDR_10                 	((uint32_t)0x00000400)
 #define VIC_IWDR_11                 	((uint32_t)0x00000800)
 #define VIC_IWDR_12                 	((uint32_t)0x00001000)
 #define VIC_IWDR_13                 	((uint32_t)0x00002000)
 #define VIC_IWDR_14                 	((uint32_t)0x00004000)
 #define VIC_IWDR_15                 	((uint32_t)0x00008000)

 #define VIC_IWDR_16                 	((uint32_t)0x00010000)
 #define VIC_IWDR_17                 	((uint32_t)0x00020000)
 #define VIC_IWDR_18                 	((uint32_t)0x00040000)
 #define VIC_IWDR_19                 	((uint32_t)0x00080000)
 #define VIC_IWDR_20                 	((uint32_t)0x00100000)
 #define VIC_IWDR_21                 	((uint32_t)0x00200000)						//低功耗唤醒清除通道21

/******* Bits definition for VIC_ISPR register**********/
 #define VIC_ISPR_0                 	((uint32_t)0x00000001)						//中断挂起使能通道0
 #define VIC_ISPR_1                		((uint32_t)0x00000002)
 #define VIC_ISPR_2                 	((uint32_t)0x00000004)
 #define VIC_ISPR_3                 	((uint32_t)0x00000008)
 #define VIC_ISPR_4                 	((uint32_t)0x00000010)
 #define VIC_ISPR_5                		((uint32_t)0x00000020)
 #define VIC_ISPR_6                 	((uint32_t)0x00000040)
 #define VIC_ISPR_7                 	((uint32_t)0x00000080)
 
 #define VIC_ISPR_8                 	((uint32_t)0x00000100)
 #define VIC_ISPR_9                		((uint32_t)0x00000200)
 #define VIC_ISPR_10                 	((uint32_t)0x00000400)
 #define VIC_ISPR_11                 	((uint32_t)0x00000800)
 #define VIC_ISPR_12                 	((uint32_t)0x00001000)
 #define VIC_ISPR_13                 	((uint32_t)0x00002000)
 #define VIC_ISPR_14                 	((uint32_t)0x00004000)
 #define VIC_ISPR_15                 	((uint32_t)0x00008000)

 #define VIC_ISPR_16                 	((uint32_t)0x00010000)
 #define VIC_ISPR_17                 	((uint32_t)0x00020000)
 #define VIC_ISPR_18                 	((uint32_t)0x00040000)
 #define VIC_ISPR_19                 	((uint32_t)0x00080000)
 #define VIC_ISPR_20                 	((uint32_t)0x00100000)
 #define VIC_ISPR_21                 	((uint32_t)0x00200000)						//中断挂起使能通道21
	
/******* Bits definition for VIC_ICPR register**********/
 #define VIC_ICPR_0                 	((uint32_t)0x00000001)						//中断挂起清除通道0
 #define VIC_ICPR_1                		((uint32_t)0x00000002)
 #define VIC_ICPR_2                 	((uint32_t)0x00000004)
 #define VIC_ICPR_3                 	((uint32_t)0x00000008)
 #define VIC_ICPR_4                 	((uint32_t)0x00000010)
 #define VIC_ICPR_5                		((uint32_t)0x00000020)
 #define VIC_ICPR_6                 	((uint32_t)0x00000040)
 #define VIC_ICPR_7                 	((uint32_t)0x00000080)
 
 #define VIC_ICPR_8                 	((uint32_t)0x00000100)
 #define VIC_ICPR_9                		((uint32_t)0x00000200)
 #define VIC_ICPR_10                 	((uint32_t)0x00000400)
 #define VIC_ICPR_11                 	((uint32_t)0x00000800)
 #define VIC_ICPR_12                 	((uint32_t)0x00001000)
 #define VIC_ICPR_13                 	((uint32_t)0x00002000)
 #define VIC_ICPR_14                 	((uint32_t)0x00004000)
 #define VIC_ICPR_15                 	((uint32_t)0x00008000)

 #define VIC_ICPR_16                 	((uint32_t)0x00010000)
 #define VIC_ICPR_17                 	((uint32_t)0x00020000)
 #define VIC_ICPR_18                 	((uint32_t)0x00040000)
 #define VIC_ICPR_19                 	((uint32_t)0x00080000)
 #define VIC_ICPR_20                 	((uint32_t)0x00100000)
 #define VIC_ICPR_21                 	((uint32_t)0x00200000)						//中断挂起清除通道21

/******* Bits definition for VIC_IABR register**********/							//中断响应状态标识通道0
 #define VIC_IABR_0                 	((uint32_t)0x00000001)						
 #define VIC_IABR_1                		((uint32_t)0x00000002)
 #define VIC_IABR_2                 	((uint32_t)0x00000004)
 #define VIC_IABR_3                 	((uint32_t)0x00000008)
 #define VIC_IABR_4                 	((uint32_t)0x00000010)
 #define VIC_IABR_5                		((uint32_t)0x00000020)
 #define VIC_IABR_6                 	((uint32_t)0x00000040)
 #define VIC_IABR_7                 	((uint32_t)0x00000080)
 
 #define VIC_IABR_8                 	((uint32_t)0x00000100)
 #define VIC_IABR_9                		((uint32_t)0x00000200)
 #define VIC_IABR_10                 	((uint32_t)0x00000400)
 #define VIC_IABR_11                 	((uint32_t)0x00000800)
 #define VIC_IABR_12                 	((uint32_t)0x00001000)
 #define VIC_IABR_13                 	((uint32_t)0x00002000)
 #define VIC_IABR_14                 	((uint32_t)0x00004000)
 #define VIC_IABR_15                 	((uint32_t)0x00008000)

 #define VIC_IABR_16                 	((uint32_t)0x00010000)
 #define VIC_IABR_17                 	((uint32_t)0x00020000)
 #define VIC_IABR_18                 	((uint32_t)0x00040000)
 #define VIC_IABR_19                 	((uint32_t)0x00080000)
 #define VIC_IABR_20                 	((uint32_t)0x00100000)
 #define VIC_IABR_21                 	((uint32_t)0x00200000)						//中断响应状态标识通道21

/******* Bits definition for VIC_IPR0 register**********/							//中断优先级设置寄存器0
 #define VIC_IPR0_PRI_0                 ((uint32_t)0x000000FF)                      //设置中断通道0优先级						
 #define VIC_IPR0_PRI_1                 ((uint32_t)0x0000FF00)
 #define VIC_IPR0_PRI_2                 ((uint32_t)0x00FF0000)
 #define VIC_IPR0_PRI_3                 ((uint32_t)0xFF000000)

/******* Bits definition for VIC_IPR1 register**********/							//中断优先级设置寄存器1
 #define VIC_IPR1_PRI_4                 ((uint32_t)0x000000FF)						//设置中断通道4优先级
 #define VIC_IPR1_PRI_5                 ((uint32_t)0x0000FF00)
 #define VIC_IPR1_PRI_6                 ((uint32_t)0x00FF0000)
 #define VIC_IPR1_PRI_7                 ((uint32_t)0xFF000000)


/******* Bits definition for VIC_IPR2 register**********/							//中断优先级通道2
 #define VIC_IPR2_PRI_8                 ((uint32_t)0x000000FF)	                    //设置中断通道8优先级					
 #define VIC_IPR2_PRI_9                 ((uint32_t)0x0000FF00)
 #define VIC_IPR2_PRI_10                ((uint32_t)0x00FF0000)
 #define VIC_IPR2_PRI_11                ((uint32_t)0xFF000000)

/******* Bits definition for VIC_IPR3 register**********/							//中断优先级寄存器3
 #define VIC_IPR3_PRI_12                ((uint32_t)0x000000FF)						//设置中断通道12优先级
 #define VIC_IPR3_PRI_13                ((uint32_t)0x0000FF00)
 #define VIC_IPR3_PRI_14                ((uint32_t)0x00FF0000)
 #define VIC_IPR3_PRI_15                ((uint32_t)0xFF000000)


/******* Bits definition for VIC_IPR4 register**********/							//中断优先级寄存器4
 #define VIC_IPR4_PRI_16                ((uint32_t)0x000000FF)                      //设置中断通道16优先级
 #define VIC_IPR4_PRI_17                ((uint32_t)0x0000FF00)
 #define VIC_IPR4_PRI_18                ((uint32_t)0x00FF0000)
 #define VIC_IPR4_PRI_19                ((uint32_t)0xFF000000)
 
/******* Bits definition for VIC_IPR5 register**********/							//中断优先级寄存器5
 #define VIC_IPR5_PRI_20                ((uint32_t)0x000000FF)                      //设置中断通道20优先级
 #define VIC_IPR5_PRI_21                ((uint32_t)0x0000FF00)
 #define VIC_IPR5_PRI_22                ((uint32_t)0x00FF0000)
 #define VIC_IPR5_PRI_23                ((uint32_t)0xFF000000)

/******* Bits definition for VIC_IPR6 register**********/							//中断优先级寄存器6
 #define VIC_IPR6_PRI_24                ((uint32_t)0x000000FF)                      //设置中断通道24优先级
 #define VIC_IPR6_PRI_25                ((uint32_t)0x0000FF00)
 #define VIC_IPR6_PRI_26                ((uint32_t)0x00FF0000)
 #define VIC_IPR6_PRI_27                ((uint32_t)0xFF000000)

/******* Bits definition for VIC_IPR7 register**********/							//中断优先级寄存器7
 #define VIC_IPR7_PRI_28                ((uint32_t)0x000000FF)                      //设置中断通道28优先级
 #define VIC_IPR7_PRI_29                ((uint32_t)0x0000FF00)
 #define VIC_IPR7_PRI_30                ((uint32_t)0x00FF0000)
 #define VIC_IPR7_PRI_31                ((uint32_t)0xFF000000)

/******* Bits definition for VIC_ISR register**********/							//中断状态寄存器
 #define VIC_ISR_VECTACTIVE             ((uint32_t)0x000001FF)                      //指示CPU当前正在处理的中断向量号
 #define VIC_ISR_VECTPENDING_0          ((uint32_t)0x00001000)                      //指示当前挂起的优先级最高的中断向量号
 #define VIC_ISR_VECTPENDING_1          ((uint32_t)0x00002000)
 #define VIC_ISR_VECTPENDING_2          ((uint32_t)0x00004000)
 #define VIC_ISR_VECTPENDING_3          ((uint32_t)0x00008000)
 #define VIC_ISR_VECTPENDING_4          ((uint32_t)0x00010000)
 #define VIC_ISR_VECTPENDING_5          ((uint32_t)0x00020000)
 #define VIC_ISR_VECTPENDING_6          ((uint32_t)0x00040000)
 #define VIC_ISR_VECTPENDING_7          ((uint32_t)0x00080000)
 #define VIC_ISR_VECTPENDING_8          ((uint32_t)0x00100000)

/******* Bits definition for VIC_IPTR register**********/							//中断优先级阈值寄存器
 #define VIC_IPTR_PRIOTHRESHOLD         ((uint32_t)0x000000FF)
 #define VIC_IPTR_PRIOTHRESHOLD_0       ((uint32_t)0x00000001)
 #define VIC_IPTR_PRIOTHRESHOLD_1       ((uint32_t)0x00000002)
 #define VIC_IPTR_PRIOTHRESHOLD_2       ((uint32_t)0x00000004)
 #define VIC_IPTR_PRIOTHRESHOLD_3       ((uint32_t)0x00000008) 
 #define VIC_IPTR_PRIOTHRESHOLD_4       ((uint32_t)0x00000010)
 #define VIC_IPTR_PRIOTHRESHOLD_5       ((uint32_t)0x00000020)
 #define VIC_IPTR_PRIOTHRESHOLD_6       ((uint32_t)0x00000040)
 #define VIC_IPTR_PRIOTHRESHOLD_7       ((uint32_t)0x00000080)
 
 #define VIC_IPTR_VECTTHRESHOLD         ((uint32_t)0x0001FF00)
 #define VIC_IPTR_VECTTHRESHOLD_0       ((uint32_t)0x00000100)
 #define VIC_IPTR_VECTTHRESHOLD_1       ((uint32_t)0x00000200)
 #define VIC_IPTR_VECTTHRESHOLD_2       ((uint32_t)0x00000400)
 #define VIC_IPTR_VECTTHRESHOLD_3       ((uint32_t)0x00000800)
 #define VIC_IPTR_VECTTHRESHOLD_4       ((uint32_t)0x00001000)
 #define VIC_IPTR_VECTTHRESHOLD_5       ((uint32_t)0x00002000)
 #define VIC_IPTR_VECTTHRESHOLD_6       ((uint32_t)0x00004000)
 #define VIC_IPTR_VECTTHRESHOLD_7       ((uint32_t)0x00008000)
 #define VIC_IPTR_VECTTHRESHOLD_8       ((uint32_t)0x00010000)
 
 #define VIC_IPTR_EN                    ((uint32_t)0x80000000)

/********************************EXINT*****************************************/	//外部中断		

/******* Bits definition for EXINT_CR register**********/							//外部中断寄存器
 #define EXINT_CR_INT0IE            	((uint16_t)0x0001)
 #define EXINT_CR_INT1IE            	((uint16_t)0x0002)
 #define EXINT_CR_KEYIE             	((uint16_t)0x0004)
 
 #define EXINT_CR_KEY0EN             	((uint16_t)0x0100)
 #define EXINT_CR_KEY1EN             	((uint16_t)0x0200)
 #define EXINT_CR_KEY2EN             	((uint16_t)0x0400)
 #define EXINT_CR_KEY3EN             	((uint16_t)0x0800)
 #define EXINT_CR_KEY4EN             	((uint16_t)0x1000)
 #define EXINT_CR_KEY5EN             	((uint16_t)0x2000)
 #define EXINT_CR_KEY6EN             	((uint16_t)0x4000)

 #define EXINT_CR_INTEDGE0              ((uint16_t)0x0018)
 #define EXINT_CR_INTEDGE0_0            ((uint16_t)0x0008)
 #define EXINT_CR_INTEDGE0_1            ((uint16_t)0x0010)

 #define EXINT_CR_INTEDGE1              ((uint16_t)0x0060)
 #define EXINT_CR_INTEDGE1_0            ((uint16_t)0x0020)
 #define EXINT_CR_INTEDGE1_1            ((uint16_t)0x0040)
 
/******* Bits definition for EXINT_SR register**********/
 #define EXINT_SR_INT0IF            	((uint16_t)0x0001)
 #define EXINT_SR_INT1IF            	((uint16_t)0x0002)
 #define EXINT_SR_KEYIF             	((uint16_t)0x0004)

/********************************GPIO**************************************/	//GPIO PT0

/******* Bits definition for GPIO0_ADR register*********/							//PT0模数设置寄存器
// #define GPIO_ADR_PTAD                ((uint16_t)0x007F)
 #define GPIO_ADR_PTAD_0              ((uint8_t)0x01)
 #define GPIO_ADR_PTAD_1              ((uint8_t)0x02)
 #define GPIO_ADR_PTAD_2              ((uint8_t)0x04)
 #define GPIO_ADR_PTAD_3              ((uint8_t)0x08)
 #define GPIO_ADR_PTAD_4              ((uint8_t)0x10)
 #define GPIO_ADR_PTAD_5              ((uint8_t)0x20)
 #define GPIO_ADR_PTAD_6              ((uint8_t)0x40)

/******* Bits definition for GPIO0_SETR register********/							//PT0端口设置寄存器
 //#define GPIO_SETR_PTSET              ((uint16_t)0x007F)
 #define GPIO_SETR_PTSET_0            ((uint8_t)0x01)
 #define GPIO_SETR_PTSET_1            ((uint8_t)0x02)
 #define GPIO_SETR_PTSET_2            ((uint8_t)0x04)
 #define GPIO_SETR_PTSET_3            ((uint8_t)0x08)
 #define GPIO_SETR_PTSET_4            ((uint8_t)0x10)
 #define GPIO_SETR_PTSET_5            ((uint8_t)0x20)
 #define GPIO_SETR_PTSET_6            ((uint8_t)0x40)
 #define GPIO_SETR_PTSET_7            ((uint8_t)0x80)
 
/******* Bits definition for GPIO0_IDR register*********/							//PT0输入数据寄存器
// #define GPIO0_IDR_PT0IN                ((uint16_t)0x007F)
 #define GPIO_IDR_PTIN_0              ((uint8_t)0x01)
 #define GPIO_IDR_PTIN_1              ((uint8_t)0x02)
 #define GPIO_IDR_PTIN_2              ((uint8_t)0x04)
 #define GPIO_IDR_PTIN_3              ((uint8_t)0x08)
 #define GPIO_IDR_PTIN_4              ((uint8_t)0x10)
 #define GPIO_IDR_PTIN_5              ((uint8_t)0x20)
 #define GPIO_IDR_PTIN_6              ((uint8_t)0x40)
 #define GPIO_IDR_PTIN_7              ((uint8_t)0x80)

/******* Bits definition for GPIO1_ODR register*********/							//PT1输出数据寄存器
 #define GPIO_ODR_PTOUT_0             ((uint8_t)0x01)
 #define GPIO_ODR_PTOUT_1             ((uint8_t)0x02)
 #define GPIO_ODR_PTOUT_2             ((uint8_t)0x04)
 #define GPIO_ODR_PTOUT_3             ((uint8_t)0x08)
 #define GPIO_ODR_PTOUT_4             ((uint8_t)0x10)
 #define GPIO_ODR_PTOUT_5             ((uint8_t)0x20)
 #define GPIO_ODR_PTOUT_6             ((uint8_t)0x40)
 #define GPIO_ODR_PTOUT_7             ((uint8_t)0x80)

/******* Bits definition for GPIO1_PUR register*********/							//PT1上拉寄存器
 #define GPIO_PUR_PTPU_0              ((uint8_t)0x01)
 #define GPIO_PUR_PTPU_1              ((uint8_t)0x02)
 #define GPIO_PUR_PTPU_2              ((uint8_t)0x04)
 #define GPIO_PUR_PTPU_3              ((uint8_t)0x08)
 #define GPIO_PUR_PTPU_4              ((uint8_t)0x10)
 #define GPIO_PUR_PTPU_5              ((uint8_t)0x20)
 #define GPIO_PUR_PTPU_6              ((uint8_t)0x40)
 #define GPIO_PUR_PTPU_7           	  ((uint8_t)0x80) 
 
/******* Bits definition for GPIO1_DSR register*********/							//PT1驱动能力设置寄存器
 #define GPIO_DSR_PTSR_0              ((uint8_t)0x01)
 #define GPIO_DSR_PTSR_1              ((uint8_t)0x02)
 #define GPIO_DSR_PTSR_2              ((uint8_t)0x04)
 #define GPIO_DSR_PTSR_3              ((uint8_t)0x08)
 #define GPIO_DSR_PTSR_4              ((uint8_t)0x10)
 #define GPIO_DSR_PTSR_5              ((uint8_t)0x20)
 #define GPIO_DSR_PTSR_6              ((uint8_t)0x40)
 #define GPIO_DSR_PTSR_7              ((uint8_t)0x80) 
 
/********************************模拟I/O***************************************/	//模拟I/O

/******* Bits definition for GPIO_ASACMR register*******/							//寄存器GPIO_ASACMR
 #define GPIO_ASACMR_A0PD              	((uint32_t)0x00000001)
 #define GPIO_ASACMR_A1PD             	((uint32_t)0x00000002)
 #define GPIO_ASACMR_A2PD              	((uint32_t)0x00000004)
 #define GPIO_ASACMR_A3PD              	((uint32_t)0x00000008)
 
 #define GPIO_ASACMR_A4PD              	((uint32_t)0x00000010)
 #define GPIO_ASACMR_A5PD              	((uint32_t)0x00000020)
 #define GPIO_ASACMR_A6PD              	((uint32_t)0x00000040)
 #define GPIO_ASACMR_A7PD              	((uint32_t)0x00000080)  
 #define GPIO_ASACMR_BGM1EN             ((uint32_t)0x00010000)
 #define GPIO_ASACMR_BGM2EN             ((uint32_t)0x00020000)
 
/******* Bits definition for GPIO_ASIOUTR register******/							//寄存器GPIO_ASIOUTR
 #define GPIO_ASIOUTR_A0IOP             ((uint16_t)0x0001)
 #define GPIO_ASIOUTR_A0ION             ((uint16_t)0x0002)
 #define GPIO_ASIOUTR_A1IOP             ((uint16_t)0x0004)
 #define GPIO_ASIOUTR_A1ION             ((uint16_t)0x0008)
 
 #define GPIO_ASIOUTR_A2IOP             ((uint16_t)0x0010)
 #define GPIO_ASIOUTR_A2ION             ((uint16_t)0x0020)
 #define GPIO_ASIOUTR_A3IOP             ((uint16_t)0x0040)
 #define GPIO_ASIOUTR_A3ION             ((uint16_t)0x0080)  
  
 #define GPIO_ASIOUTR_A4IOP             ((uint16_t)0x0100)
 #define GPIO_ASIOUTR_A4ION             ((uint16_t)0x0200)
 #define GPIO_ASIOUTR_A5IOP             ((uint16_t)0x0400)
 #define GPIO_ASIOUTR_A5ION             ((uint16_t)0x0800)    
  
/********************************SDADC*****************************************/	//SDADC 

/********* Bits definition for IA_CR register **********/							//IA_CR寄存器					
 #define IA_CR_SI                  		((uint32_t)0x00000100)
 #define IA_CR_PGIAEN              		((uint32_t)0x00000200)
 #define IA_CR_EMIS_EN                  ((uint32_t)0x00008000)
 
 #define IA_CR_IBOUT                 	((uint32_t)0xC0000000)
 #define IA_CR_IBOUT_0                 	((uint32_t)0x40000000)
 #define IA_CR_IBOUT_1                 	((uint32_t)0x80000000)
 
 #define IA_CR_OSSIGN              		((uint32_t)0x00040000)
 #define IA_CR_OSEN                		((uint32_t)0x00080000)

/******** Bits definition for SDADC_CR register ********/							//SDADC_CR寄存器
 #define SDADC_CR_SDADCEN          	    ((uint32_t)0x00000001)
 #define SDADC_CR_PAEN              	((uint32_t)0x00000002)
 #define SDADC_CR_DIEN              	((uint32_t)0x00000004)
 
 #define SDADC_CR_ADOUTS           	 	((uint32_t)0x00000040)
 
 #define SDADC_CR_P2EN              	((uint32_t)0x00800000)
 #define SDADC_CR_BUF1EN            	((uint32_t)0x01000000)
 
 #define SDADC_CR_BUF2EN            	((uint32_t)0x02000000)
 #define SDADC_CR_TEN               	((uint32_t)0x20000000)
 #define SDADC_CR_SDADCIE          	    ((uint32_t)0x80000000)
 
/******** Bits definition for EMI_CR register **********/							//EMI设置寄存器
 #define EMI_CR_EMIAEN              	((uint32_t)0x00000001)
 #define EMI_CR_EMIAOUT             	((uint32_t)0x00000008)
 #define EMI_CR_EMIA_DELEN          	((uint32_t)0x00000010)
 
 #define EMI_CR_EMIBEN              	((uint32_t)0x00010000)
 #define EMI_CR_EMIBOUT             	((uint32_t)0x00080000)
 #define EMI_CR_EMIB_DELEN          	((uint32_t)0x00100000)
 
/******** Bits definition for SDADC_SR register ********/							//SDADC状态寄存器
 #define SDADC_SR_SDADCIF          	    ((uint8_t)0x01)

/******** Bits definition for IA_CR2 register ********/							    //IA_CR2寄存器
 #define IA_CR2_SIA          	        ((uint8_t)0x01)
 
/********************************SARADC****************************************/	//SARADC

/******* Bits definition for SARADC_CR0 register *******/
 #define SARADC_CR0_SAR_ADC_EN          ((uint8_t)0x01)
 #define SARADC_CR0_SAREN           	((uint8_t)0x02)
 
/******* Bits definition for SARADC_CR1 register *******/
 #define SARADC_CR1_SAR_RST           	((uint8_t)0x01)
 
/******* Bits definition for SARADC_CR2 register *******/
 #define SARADC_CR2_SARI           		((uint8_t)0x01)
 #define SARADC_CR2_SARCONF4           	((uint8_t)0x20)
 #define SARADC_CR2_SARCONF1           	((uint8_t)0x04)
 #define SARADC_CR2_WAIT           		((uint8_t)0x40)
 #define SARADC_CR2_DROP          		((uint8_t)0x80)
 
/******* Bits definition for SARADC_CR4 register *******/ 
 #define SARADC_CR4_SARBUF_EN           ((uint8_t)0x01)
 #define SARADC_CR4_SARBUF_PH           ((uint8_t)0x02)
 #define SARADC_CR4_BUFI            	((uint8_t)0x40)
 
/******* Bits definition for SARADC_CR5 register *******/
 #define SARADC_CR5_CONIE            	((uint8_t)0x01)
 #define SARADC_CR5_RDYIE               ((uint8_t)0x04)
 #define SARADC_CR5_OVRIE               ((uint8_t)0x08)
 #define SARADC_CR5_SAMPIE              ((uint8_t)0x10)
 
/******* Bits definition for SARADC_SR register ********/
 #define SARADC_SR_CONIF                ((uint8_t)0x01)
 #define SARADC_SR_RDYIF                ((uint8_t)0x04)
 #define SARADC_SR_OVRIF                ((uint8_t)0x08)
 #define SARADC_SR_SAMPIF               ((uint8_t)0x10)


/********************************SysTick*****************************************/	//系统计数器

/******* Bits definition for SysTick_CSR register ********/							//控制和状态寄存器
 #define SysTick_CSR_ENABLE             ((uint32_t)0x00000001)	
 #define SysTick_CSR_TICKIE             ((uint32_t)0x00000002)
 #define SysTick_CSR_CLOCKSOURCE        ((uint32_t)0x00000004)
 #define SysTick_CSR_COUNTFLAG          ((uint32_t)0x00010000)
 
 #define SysTick_RVR_RELOAD             ((uint32_t)0x000FFFFF)                   //系统计数器重载值
 #define SysTick_CVR_CURRENT            ((uint32_t)0x000FFFFF)                   //系统计数器当前值
 
/****** Bits definition for SysTick_CALIBR register ******/						 //校准寄存器
 #define SysTick_CALIBR_SKEW              ((uint32_t)0x40000000)                   //表示10ms校准值
 #define SysTick_CALIBR_NOREF             ((uint32_t)0x80000000)                   //实现了外部参考时钟
 #define SysTick_CALIBR_TENMS             ((uint32_t)0x00FFFFFF)                   //系统计数器校准值
 
/**********************************TM****************************************/		//定时器寄存器

 #define TM0_CR_T0EN               		((uint16_t)0x0001)
 #define TM0_CR_T0IE               		((uint16_t)0x0080)
 #define TM0_SR_T0IF                	((uint16_t)0x0001)
 
 #define TM1_CR_CCPIE              		((uint16_t)0x0100)
 #define TM1_CR_CCPEN              		((uint16_t)0x0200)
 #define TM1_CR_CCPSEL             		((uint16_t)0x0400)
 
 #define TM1_CR_CCPM             		((uint16_t)0x7000) 
 #define TM1_CR_CCPM_0             		((uint16_t)0x1000) 
 #define TM1_CR_CCPM_1             		((uint16_t)0x2000) 
 #define TM1_CR_CCPM_2             		((uint16_t)0x4000)
 #define TM1_CR_CCPM_3             		((uint16_t)0x8000) 

/********* Bits definition for TM1_SR register *********/							//定时器1状态寄存器

 #define TM1_SR_CCPIF               	((uint16_t)0x0002)

/********* Bits definition for TM2_CR register *********/							//控制寄存器2

 #define TM2_CR_PFDEN              		((uint16_t)0x0002)

/**********************************RTC****************************************/		//RTC

/********* Bits definition for RTC_CR register *********/							//RTC控制寄存器
 #define RTC_CR_RTCIE                 	((uint8_t)0x01)
 #define RTC_CR_TAIE                	((uint8_t)0x02)
 #define RTC_CR_RTCEN                	((uint8_t)0x04)
 #define RTC_CR_TAEN         			((uint8_t)0x08)
 #define RTC_CR_N12_24          		((uint8_t)0x80)

/********* Bits definition for RTC_SR register *********/							//RTC状态寄存器
 #define RTC_SR_RTCIF                   ((uint8_t)0x01)
 #define RTC_SR_TAIF                  	((uint8_t)0x02)

/********* Bits definition for RTC_TR register *********/							//RTC状态寄存器???????????????
 #define RTC_TR_HOUR                    ((uint32_t)0x003F0000)
 #define RTC_TR_MINUTE                  ((uint32_t)0x00007F00)
 #define RTC_TR_SECOND                  ((uint32_t)0x0000007F)
 
 /********* Bits definition for RTC_DR register *********/							//RTC状态寄存器???????????????
 #define RTC_DR_YEAR                    ((uint32_t)0xFF000000)
 #define RTC_DR_MONTH                   ((uint32_t)0x001F0000)
 #define RTC_DR_WEEK                    ((uint32_t)0x00000003)
 #define RTC_DR_DAY                     ((uint32_t)0x00003F00)
 
/******* Bits definition for RTC_ALARMR register *******/							//RTC alarm寄存器
 #define RTC_ALARMR_ASECOND             ((uint32_t)0x0000007F)
 #define RTC_ALARMR_MSK1                ((uint32_t)0x00000080)
 #define RTC_ALARMR_AMINUTE             ((uint32_t)0x00007F00)
 #define RTC_ALARMR_MSK2                ((uint32_t)0x00008000)
 
 #define RTC_ALARMR_AHOUR               ((uint32_t)0x003F0000)
 #define RTC_ALARMR_A12_24              ((uint32_t)0x00400000)
 #define RTC_ALARMR_MSK3                ((uint32_t)0x00800000)
 
 #define RTC_ALARMR_AWK_ADY             ((uint32_t)0x3F000000)
 #define RTC_ALARMR_WDSEL               ((uint32_t)0x40000000)
 #define RTC_ALARMR_MSK4                ((uint32_t)0x80000000)
 
/**********************************IWDG***************************************/		//独立看门狗

/********* Bits definition for IWDG_CR register ********/							//看门狗控制寄存器
 #define IWDG_CR_WDT_CFG                ((uint32_t)0x00010000)            
 #define IWDG_CR_WDTIE                 	((uint16_t)0x8000)
 
 
 #define IWDG_CR_WDTCD                 	((uint16_t)0x00E0)
 #define IWDG_CR_WDTTM                 	((uint16_t)0x001C)
 
 #define IWDG_CR_WDTEN               	((uint16_t)0x0003) 
 #define IWDG_CR_WDTEN_1               	((uint16_t)0x0001)
 #define IWDG_CR_WDTEN_2               	((uint16_t)0x0002)

/********* Bits definition for IWDG_SR register ********/							//看门狗中断状态寄存器
 #define IWDG_SR_WDTIF                 	((uint8_t)0x01)			

/********* Bits definition for IWDG_SR register ********/							//看门狗中断状态寄存器
 #define IWDG_SETKEY_SETWDT_KEY         ((uint16_t)0xAAAA)	                        //“喂狗”
 
/**********************************WWDG***************************************/		//窗口看门狗

/********* Bits definition for WWDG_CR register ********/							//控制寄存器
 #define WWDG_CR_WWDGEN                 ((uint8_t)0x80)

/********* Bits definition for WWDG_CR register ********/							//控制寄存器
 #define WWDG_CR_T                      ((uint8_t)0x7F)
 
/********* Bits definition for WWDG_CFR register *******/							//配置寄存器
 #define WWDG_CFR_WWDGCD                ((uint16_t)0x0300)
 
/********* Bits definition for WWDG_CFR register *******/							//配置寄存器
 #define WWDG_CFR_EWI                   ((uint16_t)0x0080)
 
/********* Bits definition for WWDG_CFR register ********/							//状态寄存器
 #define WWDG_CFR_W                     ((uint16_t)0x007F)
 
 /********* Bits definition for WWDG_SR register ********/							//状态寄存器
 #define WWDG_SR_WIF                    ((uint8_t)0x01)
 
/**********************************BUZZER0************************************/		//BUZZER

/********* Bits definition for BUZ_CR0 register ********/							//蜂鸣器
 #define BUZ_CR_BUZEN                 	((uint16_t)0x0001)
 #define BUZ_CR_BUZBEN                	((uint16_t)0x0002)
 
/**********************************PWMx***************************************/		//PWD_PDM

/******** Bits definition for PWM_CR register **********/							//控制器寄存器0
 #define PWM_CR_PWMIE     				((uint8_t)0x80)
 #define PWM_CR_PWMS      				((uint8_t)0x04)
 #define PWM_CR_PMSEL     			    ((uint8_t)0x02)
 #define PWM_CR_PMEN      			    ((uint8_t)0x01)

/******** Bits definition for PWM_SR0 register *********/							//状态寄存器0
 #define PWM_SR_PWMIF     				((uint8_t)0x01)

/***********************************I2C***************************************/		//I2C通信

/******** Bits definition for I2C_CR register **********/							//控制寄存器
 #define I2C_CR_I2CEN              		((uint32_t)0x00000001)
 #define I2C_CR_GCEN               		((uint32_t)0x00000002)
 #define I2C_CR_NOSTRETCH            	((uint32_t)0x00000004)
 #define I2C_CR_START              		((uint32_t)0x00000008)
 
 #define I2C_CR_STOP              		((uint32_t)0x00000010)
 #define I2C_CR_ACK              		((uint32_t)0x00000020)
 
 #define I2C_CR_MST              		((uint32_t)0x00000100)
 #define I2C_CR_SYNC             		((uint32_t)0x00000200)
 #define I2C_CR_MRSTPM                	((uint32_t)0x00000800)
 #define I2C_CR_SWRST                   ((uint32_t)0x00008000)
 
 #define I2C_CR_STTIE                  	((uint32_t)0x00010000)
 #define I2C_CR_ADDRIE                  ((uint32_t)0x00020000)
 #define I2C_CR_BTFIE                   ((uint32_t)0x00040000)
 #define I2C_CR_ADDR10IE                ((uint32_t)0x00080000)
 
 #define I2C_CR_STOPIE                 	((uint32_t)0x00100000)
 #define I2C_CR_RXIE               		((uint32_t)0x00200000)
 #define I2C_CR_TXIE                  	((uint32_t)0x00400000)
 #define I2C_CR_BERRIE                  ((uint32_t)0x00800000)
 
 #define I2C_CR_ARLOIE                  ((uint32_t)0x01000000)
 #define I2C_CR_NACKIE                  ((uint32_t)0x02000000)
 #define I2C_CR_OVRIE                   ((uint32_t)0x04000000)
 #define I2C_CR_TMEOUTIE                ((uint32_t)0x08000000)

/******** Bits definition for I2C_ORA register *********/							//本机地址寄存器
 #define I2C_OAR_ADD                 	((uint16_t)0x0001)
 #define I2C_OAR_ADDMODE                ((uint16_t)0x8000)

/******** Bits definition for I2C_TOR register *********/							//超时设置寄存器
 #define I2C_TOR_TIMEOUTEN              ((uint32_t)0x00010000)
 
/******** Bits definition for I2C_SR register **********/							//状态寄存器
 #define I2C_SR_STT              		((uint16_t)0x0001)
 #define I2C_SR_ADDR               		((uint16_t)0x0002)
 #define I2C_SR_BTF            			((uint16_t)0x0004)
 #define I2C_SR_ADDR10              	((uint16_t)0x0008)
 
 #define I2C_SR_STOPF              		((uint16_t)0x0010)
 #define I2C_SR_RXNE              		((uint16_t)0x0020)
 #define I2C_SR_TXE              		((uint16_t)0x0040)
 #define I2C_SR_BERR              		((uint16_t)0x0080)
 
 #define I2C_SR_ARLO              		((uint16_t)0x0100)
 #define I2C_SR_NACKF            		((uint16_t)0x0200)
 #define I2C_SR_OVR                		((uint16_t)0x0400)
 #define I2C_SR_TMEOUT                  ((uint16_t)0x0800)
 
 #define I2C_SR_TRA             		((uint16_t)0x1000)
 #define I2C_SR_GENCALL            		((uint16_t)0x2000)
 #define I2C_SR_BUSY                	((uint16_t)0x4000)
 #define I2C_SR_SCLLOW                  ((uint16_t)0x8000)
 

/***********************************UART**************************************/		//UART

/******** Bits definition for UART_CR register *********/							//控制寄存器
 #define UART_CR_UE                 	((uint32_t)0x00000001)
 #define UART_CR_RE                 	((uint32_t)0x00000002)
 #define UART_CR_TE                 	((uint32_t)0x00000004)
 #define UART_CR_STOP                  	((uint32_t)0x00000100)
 #define UART_CR_PS                 	((uint32_t)0x00000200)
 #define UART_CR_PCE                 	((uint32_t)0x00000400)
 #define UART_CR_WAVE_SEL              	((uint32_t)0x00000800)
 #define UART_CR_CARRY_EN              	((uint32_t)0x00001000)
 #define UART_CR_ABREN                 	((uint32_t)0x00002000)
 #define UART_CR_WKUPEN                	((uint32_t)0x00004000)
 
 #define UART_CR_RXNEIE                	((uint32_t)0x00010000)
 #define UART_CR_TXEIE                 	((uint32_t)0x00020000)
 #define UART_CR_TCIE                  	((uint32_t)0x00040000)
 #define UART_CR_PEIE                 	((uint32_t)0x00080000)
 #define UART_CR_EIE                 	((uint32_t)0x00100000)
 #define UART_CR_WKUPIE                	((uint32_t)0x00200000)

/******** Bits definition for UART_SR register *********/							//状态寄存器
 #define UART_SR_RXNE                  	((uint16_t)0x0001)
 #define UART_SR_TXE                	((uint16_t)0x0002)
 #define UART_SR_TC                  	((uint16_t)0x0004)
 #define UART_SR_FE                  	((uint16_t)0x0008)
 #define UART_SR_ORE                  	((uint16_t)0x0010)
 #define UART_SR_NE                  	((uint16_t)0x0020)
 #define UART_SR_PE                  	((uint16_t)0x0040)
 #define UART_SR_WKUPF                 	((uint16_t)0x0080)
 #define UART_SR_ABRE                  	((uint16_t)0x0100) 
 
 
/***********************************SPI***************************************/		//SPI

/******** Bits definition for SPI_CR register **********/							//SPI控制寄存器
 #define SPI_CR_SPIEN           		((uint32_t)0x00800000)
 #define SPI_CR_NSSP            		((uint32_t)0x00400000)
 #define SPI_CR_MODFIE          		((uint32_t)0x00100000)
  
 #define SPI_CR_UDRIE           		((uint32_t)0x00080000)
 #define SPI_CR_OVRIE           		((uint32_t)0x00040000)
 #define SPI_CR_TXEIE           		((uint32_t)0x00020000)
 #define SPI_CR_RXNEIE          		((uint32_t)0x00010000)
		
 #define SPI_CR_SSOE            		((uint32_t)0x00008000)
 #define SPI_CR_SSINM           		((uint32_t)0x00004000)
 #define SPI_CR_SSI             		((uint32_t)0x00002000)
 #define SPI_CR_LSBFIRST        		((uint32_t)0x00001000)
 
 #define SPI_CR_MSTR            		((uint32_t)0x00000004)
 #define SPI_CR_CPOL            		((uint32_t)0x00000002)
 #define SPI_CR_CPHA            		((uint32_t)0x00000001)
 
 #define SPI_Clear_Bit           		((uint32_t)0x00000000)
 
/******** Bits definition for SPI_SR register **********/							//SPI状态寄存器
 #define SPI_SR_BSY             		((uint32_t)0x00000020)
 #define SPI_SR_MODF            		((uint32_t)0x00000010)
 #define SPI_SR_UDR             		((uint32_t)0x00000008)
 #define SPI_SR_OVR             		((uint32_t)0x00000004)
 #define SPI_SR_TXE             		((uint32_t)0x00000002)
 #define SPI_SR_RXNE            		((uint32_t)0x00000001)


/***********************************LCD***************************************/		//LCD

/******** Bits definition for LCD_CPMR register ********/							
 #define LCD_CPMR_CPREN                 ((uint8_t)0x01)

 #define LCD_CPMR_VLCD                  ((uint8_t)0x1E) 
 #define LCD_CPMR_VLCD_0                ((uint8_t)0x02)
 #define LCD_CPMR_VLCD_1                ((uint8_t)0x04)
 #define LCD_CPMR_VLCD_2                ((uint8_t)0x08)
 #define LCD_CPMR_VLCD_3                ((uint8_t)0x10)
 
 #define LCD_CPMR_CPRCLKS               ((uint8_t)0xE0)
 #define LCD_CPMR_CPRCLKS_0             ((uint8_t)0x20)
 #define LCD_CPMR_CPRCLKS_1             ((uint8_t)0x40)
 #define LCD_CPMR_CPRCLKS_2             ((uint8_t)0x80)
 
/******** Bits definition for LCD_CR register **********/
 #define LCD_CR_LCDEN                   ((uint16_t)0x0001)
 #define LCD_CR_LCDBL                   ((uint16_t)0x0002)
 #define LCD_CR_BIAS                	((uint16_t)0x0800)
 
/******** Bits definition for LCD_COMR register ********/							//LCD_COMR寄存器
 #define LCD_COMR_COM0                  ((uint8_t)0x01)
 #define LCD_COMR_COM1                  ((uint8_t)0x02)
 #define LCD_COMR_COM2                  ((uint8_t)0x04)
 #define LCD_COMR_COM3                	((uint8_t)0x08)
 #define LCD_COMR_COM4                  ((uint8_t)0x10)
 #define LCD_COMR_COM5                	((uint8_t)0x20)
 #define LCD_COMR_COM6                  ((uint8_t)0x40)
 #define LCD_COMR_COM7                  ((uint8_t)0x80)
 
/**********************************DBGMCU*************************************/		//DBGMCU

/******** Bits definition for DBGMCU_CR register *******/							//DBGMCU_CR寄存器		
 #define DBGMCU_CR_LPMD                 ((uint32_t)0x00000001)
 #define DBGMCU_CR_IWDG_STOP            ((uint32_t)0x00000002)
 #define DBGMCU_CR_WWDG_STOP            ((uint32_t)0x00000004)
 #define DBGMCU_CR_I2C_TMEOUT           ((uint32_t)0x00000008)
 
 #define DBGMCU_CR_BOOT_RAM             ((uint32_t)0x00010000)
 
 #define BOOT_UART1_IOMAP               ((uint32_t)0x00000800)
 #define BOOT_IWDG_STOP                 ((uint32_t)0x00000400)
 #define DBGMCU_CR_CPU_RST              ((uint32_t)0x00020000)
 #define DBGMCU_CR_MMC_HRST             ((uint32_t)0x00040000) 

/**********************************FLASH**************************************/		//闪存FLASH编程

/******* Bits definition for FLASH Keys register *******/							//FPEC键寄存器
 #define FLASH_KEY1                     ((uint32_t)0x012389AB)        
 #define FLASH_KEY2                     ((uint32_t)0x4567CDEF)                            
 
 #define FLASH_OPTKEY1                  ((uint32_t)0x012389AB)        
 #define FLASH_OPTKEY2                  ((uint32_t)0x4567CDEF)        
 
/******** Bits definition for FLASH_SR register ********/							//闪存状态寄存器
 #define FLASH_SR_BSY                  	((uint32_t)0x00000001)
 #define FLASH_SR_EOP           		((uint32_t)0x00000002) 
 
 #define FLASH_SR_PGERR                 ((uint32_t)0x00000004)
 #define FLASH_SR_WRPRTERR           	((uint32_t)0x00000008)
  
/******** Bits definition for FLASH_CR register ********/							//闪存控制寄存器
 #define FLASH_CR_PG                  	((uint32_t)0x00000001)
 #define FLASH_CR_SER           		((uint32_t)0x00000002) 
 
 #define FLASH_CR_MER                 	((uint32_t)0x00000004)
 #define FLASH_CR_DT0ER           		((uint32_t)0x00000008) 
 
 #define FLASH_CR_DT1ER                 ((uint32_t)0x00000010)
 #define FLASH_CR_OPTPG           		((uint32_t)0x00000020) 
 
 #define FLASH_CR_OPTER                 ((uint32_t)0x00000040)
 #define FLASH_CR_STRT           		((uint32_t)0x00000080) 
 
 #define FLASH_CR_LOCK                  ((uint32_t)0x00000100)
 #define FLASH_CR_OPTWRE           		((uint32_t)0x00000200) 
 
 #define FLASH_CR_ERRIE                 ((uint32_t)0x00002000)
 #define FLASH_CR_EOPIE           		((uint32_t)0x00004000)
 
 #define FLASH_CR_OBL_LAUNCH          	((uint32_t)0x00008000)

/******** Bits definition for FLASH_OBR register *******/							//选项字节寄存器
 #define FLASH_OBR_OPTERR               ((uint32_t)0x00000001)

 #define FLASH_OBR_RDPRT                ((uint32_t)0x00000006)
 #define FLASH_OBR_RDPRT1               ((uint32_t)0x00000002)        
 #define FLASH_OBR_RDPRT2               ((uint32_t)0x00000004)
 
 #define FLASH_OBR_WDG_SW               ((uint32_t)0x00004000)
 
 /******** Bits definition for FLASH_ACR register *******/							//闪存访问控制寄存器
 #define FLASH_ACR_LPEN                 ((uint32_t)0x00008000) 
  

/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/* Uncomment the line below to expanse the "assert_param" macro in the 
   Standard Peripheral Library drivers code */
/* #define USE_FULL_ASSERT    1 */

/* Exported macro ------------------------------------------------------------*/
#ifdef  USE_FULL_ASSERT

/**
  * @brief  The assert_param macro is used for function's parameters check.
  * @param  expr: If expr is false, it calls assert_failed function which reports 
  *         the name of the source file and the source line number of the call 
  *         that failed. If expr is true, it returns no value.
  * @retval None
  */
  
  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
  void assert_failed(uint8_t* file, uint32_t line);
  
#else
  #define assert_param(expr) ((void)0)
  
#endif /* USE_FULL_ASSERT */

#ifdef __cplusplus
}
#endif 


#endif /* SD93F115B_H */
/************************ (C) COPYRIGHT Hangzhou SDIC Microelectronics *****END OF FILE****/
